參數(shù)資料
型號(hào)： ADUC812BCPZ-REEL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 11.0592 MHz, MICROCONTROLLER, PQCC56
封裝： LEAD FRAME, CSP-56
文件頁(yè)數(shù)： 16/60頁(yè)
文件大?。?/td> 1276K
代理商： ADUC812BCPZ-REEL
REV. E
ADuC812
–23–
SOURCE/SINK CURRENT – mA
3
05
10
15
OUTPUT
VOLTAGE
–
V
2
1
0
Figure 21. Source and Sink Current Capability with
VREF = VDD = 3 V
To drive significant loads with the DAC outputs, external
buffering may be required, as illustrated in Figure 22.
9
ADuC812
10
Figure 22. Buffering the DAC Outputs
The DAC output buffer also features a high impedance disable
function. In the chip’s default power-on state, both DACs are
disabled, and their outputs are in a high impedance state (or
“three-state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, then a pull-down resistor must
be added to each DAC output. Assuming this resistor is in place,
the DAC outputs will remain at ground potential whenever the
DAC is disabled. However, each DAC output will still spike
briefly when power is first applied to the chip, and again when
each DAC is first enabled in software. Typical scope shots of
these spikes are given in Figure 23 and Figure 24, respectively.
200 s/DIV
AVDD – 2V/DIV
DAC OUT – 500mV/DIV
Figure 23. DAC Output Spike at Chip Power-Up
s/DIV, 1V/DIV
5
Figure 24. DAC Output Spike at DAC Enable
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