參數(shù)資料
型號: ADUC7129BSTZ126
廠商: Analog Devices Inc
文件頁數(shù): 41/92頁
文件大?。?/td> 0K
描述: IC DAS MCU ARM7 ADC/DDS 80-LQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: PLA,POR,PWM,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-LQFP
包裝: 托盤
ADuC7128/ADuC7129
Rev. 0 | Page 46 of 92
DACEN Register
Name
Address
Default Value
Access
DACEN
0xFFFF06B8
0x00
R/W
Table 50. DACEN MMR Bit Designations
Bit
Description
7:1
Reserved.
0
Set to 1 by the user to enable DAC mode.
Set to 0 by the user to enable DDS mode.
DACDAT Register
Name
Address
Default Value
Access
DACDAT
0xFFFF06B4
0x0000
R/W
Table 51. DACDAT MMR Bit Designations
Bit
Description
15:10
Reserved.
9:0
10-bit data for DAC.
The DACDAT MMR controls the output of the DAC. The data
written to this register is a ±9-bit signed value. This means that
0x0000 represents midscale, 0x0200 represents zero scale, and
0x01FF represents full scale.
DACEN and DACDAT require key access. To write to these
MMRs, use the sequences shown in Table 52.
Table 52. DACEN and DACDAT Write Sequences
DACEN
DACDAT
DACKEY0 = 0x07
DACEN = user value
DACDAT = user value
DACKEY1 = 0xB9
DDS
The DDS is used to generate a digital sine wave signal for the
DAC on the ADuC7128/ADuC7129. It can be enabled into
a free running mode by the user.
Both the phase and frequency can be controlled.
Table 53. DDSCON MMR Bit Designations
Bit
Description
7:6
Reserved.
5
DDS Output Enable.
Set by user to enable the DDS output. This has an effect only if the DDS is selected in DACCON.
Cleared by user to disable the DDS output.
4
Reserved.
Binary Divide Control.
DIV
Scale Ratio
0000
0.000
0001
0.125
0010
0.250
0011
0.375
0100
0.500
0101
0.625
0110
0.750
0111
0.875
3:0
1xxx
1.000
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