ADC Clock Speed (fADC = F<" />
參數(shù)資料
型號: ADUC7129BSTZ126
廠商: Analog Devices Inc
文件頁數(shù): 28/92頁
文件大?。?/td> 0K
描述: IC DAS MCU ARM7 ADC/DDS 80-LQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: PLA,POR,PWM,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-LQFP
包裝: 托盤
ADuC7128/ADuC7129
Rev. 0 | Page 34 of 92
Table 33. ADCCON MMR Bit Designations
Bit
Value
Description
12:10
ADC Clock Speed (fADC = FCORE, Conversion = 19 ADC Clocks + Acquisition Time).
000
fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz.
001
fADC/2 (default value).
010
fADC/4.
011
fADC/8.
100
fADC/16.
101
fADC/32.
9:8
ADC Acquisition Time (Number of ADC Clocks).
00
2 clocks.
01
4 clocks.
10
8 clocks (default value).
11
16 clocks.
7
Enable Conversion.
Set by user to enable conversion mode.
Cleared by user to disable conversion mode.
6
Reserved. This bit should be set to 0 by the user.
5
ADC Power Control.
Set by user to place the ADC in normal mode. The ADC must be powered up for at least 5 μs before it converts correctly.
Cleared by user to place the ADC in power-down mode.
Conversion Mode.
00
Single-ended Mode.
01
Differential Mode.
10
Pseudo Differential Mode.
4:3
11
Reserved.
Conversion Type.
000
Enable CONVST pin as a conversion input.
001
Enable Timer1 as a conversion input.
010
Enable Timer0 as a conversion input.
011
Single Software Conversion. Set to 000 after conversion. Bit 7 of ADCCON MMR should be cleared after starting a single
software conversion to avoid further conversions triggered by the CONVST pin.
100
Continuous Software Conversion.
101
PLA Conversion.
110
PWM Conversion.
2:0
Other
Reserved.
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