參數(shù)資料
型號(hào)： ADSP-TS203SABP-050
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP FLOAT/FIXED 500MHZ 576BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點(diǎn)/浮點(diǎn)
接口： 主機(jī)接口，連接端口，多處理器
時(shí)鐘速率： 500MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 576-BGA-ED（25x25）
包裝： 托盤
其它名稱： ADSP-TS203SABP050
ADSP-TS203SABP050-ND
Rev. D
|
Page 14 of 48
|
May 2012
Table 7. Pin Definitions—External Port DMA/Flyby
Signal
Type
Term
Description
DMAR3–0
I/A
epu
DMA Request Pins. Enable external I/O devices to request DMA services from the
processor. In response to DMARx, the processor performs DMA transfers according
to the DMA channel’s initialization. The processor ignores DMA requests from unini-
tialized channels.
IOWR
O/T
(pu_0)
nc
I/O Write. When a processor DMA channel initiates a flyby mode read transaction,
the processor asserts the IOWR signal during the data cycles. This assertion makes
the I/O device sample the data instead of the TigerSHARC.
IORD
O/T
(pu_0)
nc
I/O Read. When a processor DMA channel initiates a flyby mode write transaction,
the processor asserts the IORD signal during the data cycle. This assertion with the
IOEN makes the I/O device drive the data instead of the TigerSHARC.
IOEN
O/T
(pu_0)
nc
I/O Device Output Enable. Enables the output buffers of an external I/O device for
fly-by transactions between the device and external memory. Active on flyby
transactions.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
Type
Term
Description
MSSD3–0
I/O/T
(pu_0)
nc
Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the
processor accesses SDRAM memory space. MSSD3–0 are decoded memory address
pins that are asserted whenever the processor issues an SDRAM command cycle
(access to ADDR31:30 = 0b01—except reserved spaces shown in Figure 2 on
Page 6). In a multiprocessor system, the master processor drives MSSD3–0.
RAS
I/O/T
(pu_0)
nc
Row Address Select. When sampled low, RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation
to execute according to SDRAM specification.
CAS
I/O/T
(pu_0)
nc
Column Address Select. When sampled low, CAS indicates that a column address is
valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of
operation to execute according to the SDRAM specification.
LDQM
O/T
(pu_0)
nc
Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. LDQM is valid on SDRAM transactions when CAS is asserted, and inactive
on read transactions.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
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