參數(shù)資料
型號(hào)： ADSP-TS203SABP-050
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP FLOAT/FIXED 500MHZ 576BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點(diǎn)/浮點(diǎn)
接口： 主機(jī)接口，連接端口，多處理器
時(shí)鐘速率： 500MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 576-BGA-ED（25x25）
包裝： 托盤
其它名稱： ADSP-TS203SABP050
ADSP-TS203SABP050-ND
Rev. D
|
Page 19 of 48
|
May 2012
When default configuration is used, no external resistor is
needed on the strap pins. To apply other configurations, a 500 Ω
resistor connected to VDD_IO is required. If providing external
pull-downs, do not strap these pins directly to VSS; the strap
pins require 500 Ω resistor straps.
All strap pins are sampled on the rising edge of RST_IN (deas-
sertion edge). Each pin latches the strapped pin state (state of
the strap pin at the rising edge of RST_IN). Shortly after deas-
sertion of RST_IN, these pins are reconfigured to their normal
functionality.
These strap pins have an internal pull-down resistor, pull-up
resistor, or no-resistor (three-state) on each pin. The resistor
type, which is connected to the I/O pad, depends on whether
RST_IN is active (low) or if RST_IN is deasserted (high).
Table 17 shows the resistors that are enabled during active reset
and during normal operation.
SYS_REG_WE
I (pd_0)
BUSLOCK
SYSCON and SDRCON Write Enable.
0 = one-time writable after reset (default)
1 = always writable
TM1
I (pu)
L1BCMPO
Test Mode 1. Do not overdrive default value during reset.
TM2
I (pu)
TM2
Test Mode 2. Do not overdrive default value during reset.
TM3
I (pu)
TM3
Test Mode 3. Do not overdrive default value during reset.
Table 16. Pin Definitions—I/O Strap Pins (Continued)
Signal
Type (at
Reset)
On Pin …
Description
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Table 17. Strap Pin Internal Resistors—Active Reset
(RST_IN = 0) vs. Normal Operation (RST_IN = 1)
Pin
RST_IN = 0
RST_IN = 1
BMS
(pd_0)
(pu_0)
BM
(pd)
Driven
TMR0E
(pd)
Driven
BUSLOCK
(pd_0)
(pu_0)
L1BCMPO
(pu)
Driven
TM2
(pu)
Driven
TM3
(pu)
Driven
pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ;
pd_0 = internal pull-down 5 kΩ on processor ID = 0;
pu_0 = internal pull-up 5 kΩ on processor ID = 0
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