參數(shù)資料
型號(hào)： ADSP-TS203SABP-050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁數(shù)： 9/48頁
文件大?。?/td> 2017K
代理商： ADSP-TS203SABP-050
ADSP-TS203S
Rev. C
|
Page 17 of 48
|
December 2006
Table 11. Pin Definitions—Link Ports
Signal
Type
Term
Description
LxDATO3–0P
O
nc
Link Ports 1–0 Data 1–0 Transmit LVDS P
LxDATO3–0N
O
nc
Link Ports 1–0 Data 1–0 Transmit LVDS N
LxCLKOUTP
O
nc
Link Ports 1–0 Transmit Clock LVDS P
LxCLKOUTN
O
nc
Link Ports 1–0 Transmit Clock LVDS N
LxACKI
I (pd)
nc
Link Ports 1–0 Receive Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
LxBCMPO
O (pu)
nc
Link Ports 1–0 Block Completion. When the transmission is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed. The pull-up
resistor is present on L0BCMPO only. At reset, the L1BCMPO pin is a strap pin. For more
information, see Table 16 on Page 19.
LxDATI3–0P
I
VDD_IO
Link Ports 1–0 Data 3–0 Receive LVDS P
LxDATI3–0N
I
VDD_IO
Link Ports 1–0 Data 3–0 Receive LVDS N
LxCLKINP
I/A
VDD_IO
Link Ports 1–0 Receive Clock LVDS P
LxCLKINN
I/A
VDD_IO
Link Ports 1–0 Receive Clock LVDS N
LxACKO
O
nc
Link Ports 1–0 Transmit Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
LxBCMPI
I (pd_l)
VSS
Link Ports 1–0 Block Completion. When the reception is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω; pd_l = internal pull-down 50 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
Table 12. Pin Definitions—Impedance Control, Drive Strength Control, and Regulator Enable
Signal
Type
Term
Description
CONTROLIMP0
CONTROLIMP1
I (pd)
I (pu)
na
Impedance Control. As shown in Table 13, the CONTROLIMP1–0 pins select between
normal driver mode and A/D driver mode. When using normal mode (recommended),
the output drive strength is set relative to maximum drive strength according to
Table 14. When using A/D mode, the resistance control operates in the analog mode,
where drive strength is continuously controlled to match a specific line impedance as
shown in Table 14.
DS2, 0
DS1
I (pu)
I (pd)
na
Digital Drive Strength Selection. Selected as shown in Table 14. For drive strength calcu-
lation, see Output Drive Currents on Page 35. The drive strength for some pins is preset,
not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%)
include: CPA, DPA, TDO, EMU, and RST_OUT. The drive strength for the ACK pin is always
×2 drive strength 7 (100%).
ENEDREG
I (pu)
VSS
Connect the ENEDREG pin to VSS. Connect the VDD_DRAM pins to a properly decoupled
DRAM power supply.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
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