參數(shù)資料
型號(hào)： ADSP-TS203SABP-050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁(yè)數(shù)： 5/48頁(yè)
文件大小： 2017K
代理商： ADSP-TS203SABP-050
ADSP-TS203S
Rev. C
|
Page 13 of 48
|
December 2006
Table 5. Pin Definitions—External Port Bus Controls
Signal
Type
Term
Description
ADDR31–0
I/O/T
(pu_ad)
nc
Address Bus. The DSP issues addresses for accessing memory and peripherals on
these pins. In a multiprocessor system, the bus master drives addresses for accessing
internal memory or I/O processor registers of other ADSP-TS203S processors. The DSP
inputs addresses when a host or another DSP accesses its internal memory or I/O
processor registers.
DATA31–0
I/O/T
(pu_ad)
nc
External Data Bus. The DSP drives and receives data and instructions on these pins.
Pull-up or pull-down resistors on unused DATA pins are unnecessary.
RD
I/O/T
(pu_0)
epu1
Memory Read. RD is asserted whenever the DSP reads from any slave in the system,
excluding SDRAM. When the DSP is a slave, RD is an input and indicates read trans-
actions that access its internal memory or universal registers. In a multiprocessor
system, the bus master drives RD. RD changes concurrently with ADDR pins.
WRL
I/O/T
(pu_0)
epu1
Write Low. WRL is asserted when the ADSP-TS203S processor writes to the external
bus (host, memory, or DSP). An external master (host or DSP) asserts WRL for writing
to a DSP’s internal memory. In a multiprocessor system, the bus master drives WRL.
WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL is an input
and indicates write transactions that access its internal memory or universal registers.
ACK
I/O/T/OD
(pu_od_0)
epu1
Acknowledge. External slave devices can deassert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers, and other periph-
erals on the data phase. The DSP can deassert ACK to add wait states to read and write
accesses of its internal memory. The pull-up is 50
Ω on low-to-high transactions and
is 500
Ω on all other transactions.
BMS
O/T
(pu_0)
na
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During
reset, the DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multipro-
cessor system, the DSP bus master drives BMS. For details, see Reset and Booting on
Page 9 and the EBOOT signal description in Table 16 on Page 19.
MS1–0
O/T
(pu_0)
nc
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0
or 1, respectively. MS1–0 are decoded memory address pins that change concurrently
with ADDR pins. When ADDR31:27 = 0b00110, MS0 is asserted. When ADDR31:27 =
0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1–0.
MSH
O/T
(pu_0)
nc
Memory Select Host. MSH is asserted whenever the DSP accesses the host address
space (ADDR31 = 0b1). MSH is a decoded memory address pin that changes concur-
rently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH.
BRST
I/O/T
(pu_0)
epu
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading
or writing data associated with consecutive addresses. A slave device can ignore
addresses after the first one and increment an internal address counter after each
transfer. For host-to-DSP burst accesses, the DSP increments the address automati-
cally while BRST is asserted.
TM4
I/O/T
epu
Test Mode 4. Must be pulled up to VDD_IO with a 5 kΩ resistor.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
1 This external pull-up may be omitted for the ID = 000 TigerSHARC processor.
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