參數(shù)資料
型號： ADSP-TS203SABP-050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁數(shù)： 21/48頁
文件大小： 2017K
代理商： ADSP-TS203SABP-050
Rev. C
|
Page 28 of 48
|
December 2006
ADSP-TS203S
ENEDREG
Static Pins—Must Be Connected to VSS
——
—
STRAP SYS9, 10
Strap Pins
1.5
0.5
——
SCLK
JTAG SYS
11, 12
JTAG System Pins
+2.5
+10.0
+12.0
–1.0
—
TCK
1 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
2 For input specifications on FLAG3–0 pins, see Table 21.
3 These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.
4 For additional requirement details, see Reset and Booting on Page 9.
5 RST_IN clock reference is the falling edge of SCLK.
6 TDO output clock reference is the falling edge of TCK.
7 Reference clock depends on function.
8 These pins may change only during reset; recommend connecting it to V
DD_IO/VSS.
9 STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, TM2, and TM3.
10Specifications applicable during reset only.
11JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, BMS, IOWR, IORD, BM, EMU, SDA10, IOEN,
BUSLOCK, TMR0E, DATA31–0, ADDR31–0, RD, WRL, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0, L1DATOP3–0,
L1DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L0ACKI, L1ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L0CLKINP,
L0CLKINN, L1CLKINP, L1CLKINN, L0ACKO, L1ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L0BCMPI, L1BCMPI, ID2–0, CTRL_IMPD1–0, SCLKRAT2–0, DS2–0,
ENEDREG, TM2, TM3, TM4.
12JTAG system output timing clock reference is the falling edge of TCK.
Figure 15. General AC Parameters Timing
Table 29. AC Signal Specifications (Continued)
(All values in this table are in nanoseconds.)
Name
Description
In
put
S
e
tu
p
(M
in
)
In
put
Hold
(M
in
)
Ou
tp
u
tV
a
li
d
(M
a
x
)
Ou
tp
u
tH
o
ld
(M
in
)
Ou
tp
u
tEn
ab
le
(M
in
)1
Ou
tpu
tDi
sab
le
(M
a
x
)1
Re
fe
re
nce
Cl
ock
REFERENCE
CLOCK
INPUT
SIGNAL
OUTPUT
SIGNAL
THREE-
STATE
OUTPUT
VALID
OUTPUT
HOLD
OUTPUT
ENABLE
OUTPUT
DISABLE
INPUT
HOLD
INPUT
SETUP
1.25V
tSCLK OR tTCK
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