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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 21 of 68
|
January 2011
Table 8 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Clock Related Operating Conditions
Table 9 describes the timing requirements for the processor
clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as
not to exceed the maximum core clock and system clock.
Table 10 describes phase-locked loop operating conditions.
Table 8. TWI_DT Field Selections and VDDEXT/VBUSTWI
TWI_DT
VDDEXT Nominal
VBUSTWI Minimum
VBUSTWI Nominal
VBUSTWI Maximum
Unit
000 (default)
3.3
2.97
3.3
3.63
V
001
1.8
1.7
1.8
1.98
V
010
2.5
2.97
3.3
3.63
V
011
1.8
2.97
3.3
3.63
V
100
3.3
4.5
5
5.5
V
101
1.8
2.25
2.5
2.75
V
110
2.5
2.25
2.5
2.75
V
111 (reserved)
——
———
Table 9. Core Clock (CCLK) Requirements
Parameter
Nominal
Voltage Setting
Maximum
Unit
fCCLK
Core Clock Frequency (VDDINT =1.33 V Minimum, All Models)
1.400 V
400
MHz
Core Clock Frequency (VDDINT =1.23 V Minimum, Industrial/Commercial Models)
1.300 V
300
MHz
Core Clock Frequency (VDDINT = 1.14 V Minimum, Industrial Models Only)
1.200 V
200
MHz
Core Clock Frequency (VDDINT = 1.10 V Minimum, Commercial Models Only)
1.150 V
200
MHz
Table 10. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
(Commercial/Industrial Models)
72
Instruction Rate
1
MHz
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
84
Instruction Rate1
MHz
Table 11. SCLK Conditions
V
DDEXT/VDDMEM
1.8 V Nominal
V
DDEXT/VDDMEM
2.5 V or 3.3 V Nominal
Parameter1
Max
Unit
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
Minimum)
80
100
MHz
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT < 1.230 V )
80
MHz
1 f
SCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 28 on Page 31.
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