參數(shù)資料
型號: ADSP-21160M
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: DSP微機
文件頁數(shù): 6/53頁
文件大?。?/td> 696K
代理商: ADSP-21160M
ADSP-21160M
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REV. 0
transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automati-
cally transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
multichannel mode. The serial ports can operate with lit-
tle-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable
synchronization and transmit modes as well as optional
μ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.
Host Processor Interface
The ADSP-21160M host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160M
s external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M
s external bus with host bus request
(HBR), host but grant (HBG), ready (REDY), acknowledge
(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160M,
and can access the DMA channel setup and mailbox regis-
ters. Vector interrupt support provides efficient execution
of host commands.
Program Booting
The internal memory of the ADSP-21160M can be booted
at system power-up from an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
for booting.
Phased Locked Loop
The ADSP-21160M uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
port operates.
Power Supplies
The ADSP-21160M has separate power supply connections
for the internal (V
DDINT
), external (V
DDEXT
), and analog
(AV
DD
/AGND) power supplies. The internal and analog
supplies must meet the 2.5 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same supply.
Note that the analog supply (AV
DD
) powers the
ADSP-21160M
s clock generator PLL. To produce a stable
clock, the system must provide an external circuit to filter
the power input to the AV
DD
pin. Place the filter as close as
possible to the pin. For an example circuit, see
Figure 5
. To
prevent noise coupling, use a wide trace for the analog
ground (AGND) signal and install a decoupling capacitor
as close as possible to the pin.
Figure 4. Shared Memory Multiprocessing System
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ADSP-21160N 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21160NCB-100 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI,以太網(wǎng),RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應商設備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21160NCB-TBD 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer