參數(shù)資料
型號(hào): ADSP-21160M
廠(chǎng)商: Analog Devices, Inc.
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: DSP Microcomputer
中文描述: DSP微機(jī)
文件頁(yè)數(shù): 37/53頁(yè)
文件大?。?/td> 696K
代理商: ADSP-21160M
37
REV. 0
ADSP-21160M
Serial Ports
To determine whether communication is possible between
two devices at clock speed n, the following specifications
must be confirmed: 1) frame sync delay and frame sync
setup and hold, 2) data delay and data setup and hold, and
3) SCLK width.
Table 21. Serial Ports
External Clock
Parameter
Timing Requirements:
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
Min
Max
Unit
TFS/RFS Setup Before TCLK/RCLK
1
TFS/RFS Hold After TCLK/RCLK
1,2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
TCLK/RCLK Width
TCLK/RCLK Period
3.5
4
1.5
4
14
2t
CCLK
ns
ns
ns
ns
ns
ns
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 22. Serial Ports
Internal Clock
Parameter
Timing Requirements:
t
SFSI
t
HFSI
t
SDRI
t
HDRI
Min
Max
Unit
TFS Setup Before TCLK
1
; RFS Setup Before RCLK
1
TFS/RFS Hold After TCLK/RCLK
1,2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
8
1
6.5
3
ns
ns
ns
ns
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 23. Serial Ports
External or Internal Clock
Parameter
Switching Characteristics:
t
DFSE
t
HOFSE
Min
Max
Unit
RFS Delay After RCLK (Internally Generated RFS)
1
RFS Hold After RCLK (Internally Generated RFS)
1
13
ns
ns
3
1
Referenced to drive edge.
Table 24. Serial Ports
External Clock
Parameter
Switching Characteristics:
t
DFSE
t
HOFSE
t
DDTE
t
HDTE
Min
Max
Unit
TFS Delay After TCLK (Internally Generated TFS)
1
TFS Hold After TCLK (Internally Generated TFS)
1
Transmit Data Delay After TCLK
1
Transmit Data Hold After TCLK
1
13
ns
ns
ns
ns
3
16
0
1
Referenced to drive edge.
Table 25. Serial Ports
Internal Clock
Parameter
Switching Characteristics:
t
DFSI
t
HOFSI
Min
Max
Unit
TFS Delay After TCLK (Internally Generated TFS)
1
TFS Hold After TCLK (Internally Generated TFS)
1
4.5
ns
ns
1.5
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