參數(shù)資料
型號: ADS8342IBPFBTG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封裝: GREEN, PLASTIC, TQFP-48
文件頁數(shù): 9/28頁
文件大?。?/td> 1129K
代理商: ADS8342IBPFBTG4
ADS8342
SBAS277 – MAY 2003
www.ti.com
17
The external reference voltage sets the analog input
voltage range. The ADS8342 can operate with a reference
between 2.0V and 2.55V. There are several important
implications to this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the least significant bit (LSB) size and is
equal to the reference voltage divided by 32,768. This
means that any offset or gain error inherent in the ADC
appears to increase (in terms of LSB size) as the reference
voltage is reduced. For a reference voltage of 2V, the value
of the LSB is 61.035
V. For a reference voltage of 2.5V, the
LSB is 76.294
V.
The noise inherent in the converter also appears to
increase with a lower LSB size. With a 2.5V reference, the
internal noise of the converter typically contributes only
1.5LSBs peak-to-peak of potential error to the output code.
When the external reference is 2.0V, the potential error
contribution from the internal noise is larger (2LSBs). The
errors due to the internal noise are Gaussian in nature and
can be reduced by averaging consecutive conversion
results.
To obtain optimum performance from the ADS8342, a
0.22
F ceramic capacitor must be connected as close as
possible to the REFIN pin, to reduce noise coupling into
this high impedance input. Because the reference voltage
is internally buffered, a high output impedance reference
source can be used without the need for an additional
operational amplifier to drive the REFIN pin.
NOISE
The transition noise of the ADS8342 is extremely low, as
shown in Figure 25 and Figure 26. These histograms were
generated by applying a low-noise dc input and initiating
8192 conversions. The digital output of the ADC varies in
output code due to the internal noise of the ADS8342. This
is true for all 16-bit, SAR-type ADCs. Using a histogram to
plot the output codes, the distribution should appear
bell–shaped with the peak of the bell curve representing
the nominal code for the input value. The
±1σ, ±2σ, and
±3σ distributions will represent the 68.3%, 95.5%, and
99.7%, respectively, of all codes. The transition noise is
calculated by dividing the number of codes measured by
6, and yields the
±3σ distribution, or 99.7%, of all codes.
Statistically, up to three codes could fall outside the
distribution when executing 1000 conversions. The
ADS8342, with less than three output codes for the
±3σ
distribution, will yield <
±0.5LSBs of transition noise.
Remember, to achieve this low-noise performance, the
peak-to-peak noise of the input signal and reference must
be < 50
V.
Figure 25. Histogram of 8192 Conversions of a
DC Input at Code Transition
Figure 26. Histogram of 8192 Conversions of a
DC Input at Code Center
Note that the effective number of bits (ENOB) figure is
calculated based on the ADC signal-to-noise (SNR) ratio
with a 10kHz, –0.2dB input signal. SNR is related to ENOB
as follows:
SNR = 6.02
× ENOB + 1.76
AVERAGING
The noise of the ADC can be compensated by averaging
the digital codes. By averaging conversion results,
transition noise is reduced by a factor of 1/
√n, where n is
the number of averages. For example, averaging four
conversion results will reduce the transition noise from
±0.5LSB to ±0.25LSB. Averaging should only be used for
input signals with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the
signal-to-noise ratio will improve by 3dB.
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