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參數(shù)資料
| 型號(hào)： | ADS8342IBPFBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 1129K |
| 代理商： | ADS8342IBPFBTG4 |
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ADS8342
SBAS277 – MAY 2003
www.ti.com
18
DIGITAL INTERFACE
SIGNAL LEVELS
The ADS8342 digital interface accommodates different
logic levels. The digital interface circuit is designed to
operate using 2.7V to 5.5V logic levels. When the
ADS8342 interface power-supply voltage is in the range of
4.5V to 5.5V (5V logic level), the ADS8342 can be
connected directly to another 5V CMOS integrated circuit.
If the ADS8342 interface power-supply voltage is in the
range of 2.7V to 3.6V, the ADS8342 can be connected
directly to another 3.3V LVCMOS integrated circuit. Note
that digital inputs must not exceed BVDD by more than
+0.3V.
TIMING AND CONTROL
The ADS8342 uses a parallel control interface consisting
of the following digital input pins: CS, RD, CONV, CLK,
BYTE, A0, A1, CLKDIV0, and CLKDIV1. The following
pins are digital outputs: BUSY, and DB1 to DB15. See
Figure 2 (page 10) for a typical timing diagram.
The CS input enables the digital interface of the ADS8342.
CS and CONV start a conversion and CS and RD allow the
output data to be read.
BYTE controls the data output bus width. A0 and A1 select
the input MUX channel and CLKDIV0 and CLKDIV1 select
the internal clock divider ratio.
The ADS8342 needs an external clock, CLK ( pin 11), that
controls the conversion rate of the ADC. A typical conversion
cycle takes 20 clock cycles: 17 for conversion and 3 for signal
acquisition. A 250kHz sample rate can be achieved with a
5MHz external clock and a clock divider ratio of 1. This
corresponds to a 4
s maximum throughput period.
The following list describes some of the pins used:
CLK—An external clock must be provided to the ADS8342 via
the digital input pin CLK. The frequency of the externally
provided clock can be divided down inside the ADS8342 to
provide a slower internal clock frequency for the ADS8342.
The maximum internal clock frequency is 5MHz. The
minimum internal clock period is 200ns (see Figure 2, tC1).
The clock duty cycle (HIGH/LOW) for an external clock of
5MHz can range up to 40/60 to 60/40.
CLKDIVx—The CLKDIVx digital input pins are decoded to
select the clock frequency divider ratio that divides the
external clock frequency for use internal to the ADS8342. This
feature is useful for systems where a clock rate higher than
5MHz is available. For example, if a digital signal processor
(DSP) uses a 20MHz clock, it is possible to set up the internal
clock divider of the ADS8342 to divide the input clock
frequency by four, to provide an internal clock speed of 5MHz.
Table 2 shows the maximum applicable external clock
frequency as a function of the CLKDIV0 and CLKDIV1 signals.
Table 2. Clock Divider Selection
CLOCK
RATIO
MAX INPUT
FREQUENCY
INTERNAL
FREQUENCY
CLKDIV1
CLKDIV0
(1:n)
(MHz)
0
1
5
0
1
2
10
5
1
0
4
20
5
1
8
20
2.5
Note that all timing diagrams and specifications are
referenced to a clock divider ratio of 1:1 and an external
clock frequency of 5MHz. For higher clock input
frequencies, there will be a minor increase in power
consumption and a possible increase in noise.
BUSY—The digital output signal, BUSY, provides an external
indication that a conversion is taking place. BUSY goes high a
maximum of 70ns after a conversion is initiated (see Figure 2,
tD3) and remains high until the end of the conversion. When
BUSY goes low at the end of the conversion, the data from the
conversion in progress is latched into the ADC output registers
and is ready to be read. The BUSY signal remains low until
another conversion is started by bringing
CS and CONV low.
A0 AND A1—The digital inputs, A0 and A1, are MUX address
lines used to select the positive analog input MUX channel to
use for conversion. When a conversion is started with CS and
CONV, the Ax inputs are latched into registers on the rising
edge of CS or CONV. The latched MUX inputs control the state
of the MUX for the next conversion following the current
conversion. At the end of the conversion, the analog input
returns to the sampling mode and samples the MUX channel
that was latched during the previous conversion start.
BYTE—The BYTE signal can be used in conjunction with the
RD signal to control the output data bus width. If BYTE is
held low, the ADS8342 operates in 16-bit output mode and
the output data is read on pins DB15 to DB0. When an 8-bit
bus interface is required, the 16-bit output word can be
read using eight data lines by toggling the RD and BYTE
signals. The lower eight data output bits are read on output
pins D7 to D0 when BYTE is low. The higher eight data
output bits are read on the same output pins, D7 to D0,
when BYTE is high (see Figure 2).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8342IPFB | 制造商:Texas Instruments 功能描述: |
| ADS8342IPFBR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8342IPFBRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8342IPFBT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8342IPFBTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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