參數(shù)資料
型號: ADS8342IBPFBTG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封裝: GREEN, PLASTIC, TQFP-48
文件頁數(shù): 8/28頁
文件大?。?/td> 1129K
代理商: ADS8342IBPFBTG4
ADS8342
SBAS277 – MAY 2003
www.ti.com
16
±
Figure 22. Pseudo-Differential Input Mode of the ADS8342
The range of the COMMON input is limited to –0.1V to
+0.1V. Due to this, the differential input can be used to
reject signals that are common to both inputs in the
specified range. Thus, the COMMON input is best used to
sense a remote signal ground that may move slightly with
respect to the local ground potential.
The general method for driving the analog input of the
ADS8342 is shown in Figure 23 and Figure 24. The
COMMON input is held at the common-mode voltage. The
AINx input swings from COMMON – VREF to COMMON +
VREF, and the peak-to-peak amplitude is 2 x VREF.
Figure 23. Method for Driving the ADS8342
The input current required by the analog inputs depends
on a number of factors, such as sample rate, input voltage,
and source impedance. Essentially, the current into the
ADS8342 analog inputs charges the internal capacitor
array during the sample period. After this capacitance has
been fully charged, there is no further input current. The
source of the analog input voltage must be able to charge
the input capacitance (20pF) to a 16-bit settling level within
3 clock cycles (600ns). When the converter goes into hold
mode, the input impedance is greater than 1G
.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the
COMMON input should not drop below AGND – 0.1V, or
exceed AGND + 0.1V. The AINx input must always remain
within the range of COMMON – VREF to COMMON + VREF.
To minimize noise, low bandwidth input signals or
low-pass filters must be used. In each case, care must be
taken to ensure that the output impedance of the sources
driving the AINx and COMMON inputs are matched.
Often, a small capacitor (100pF) between the positive and
negative inputs helps to match their impedance. To obtain
good performance from the ADS8342, the input circuit
from Figure 24 is recommended.
Figure 24. Single-Ended Method of Interfacing
the ADS8342
REFERENCE AND REFGND INPUTS
The reference input of the ADS8342, REFIN, is buffered
with an internal reference amplifier. The reference
amplifier buffers the reference input from the switching
currents needed to charge and discharge the internal
capacitor DAC (CDAC), and therefore, the need to provide
an external reference capable of supplying these
switching currents is eliminated.
The reference ground input, REFGND, is connected directly
to the CDAC. During the conversion, currents to charge and
discharge the CDAC flow through the REFGND pin. For that
reason, it is important that REFGND has a low-impedance
connection to ground.
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