參數(shù)資料
型號(hào)： ADS8342IBPFBTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 1129K
代理商： ADS8342IBPFBTG4
ADS8342
SBAS277 – MAY 2003
www.ti.com
15
THEORY OF OPERATION
The ADS8342 is a classic successive approximation
register (SAR) analog–to–digital converter (ADC). The
architecture is based on capacitive charge redistribution
that inherently includes a sample–and–hold function. The
converter is fabricated on a 0.5
m CMOS process. The
architecture and process allow the ADS8342 to acquire
and convert an analog signal at up to 250,000 conversions
per second, while consuming less than 200mW.
The ADS8342 requires an external reference, an external
clock, and a dual power source (
±5V). When a digital
interface voltage (BVDD) different from +5V is desired, a
triple power source is required (
±5V and BVDD). The
external reference can be between 2V and 2.55V. The
value of the reference voltage directly sets the range of the
analog input.
The external clock can vary between 500kHz (25kHz
throughput)
and
5MHz
(250kHz
throughput).
The
minimum clock frequency is set by the leakage on the
internal capacitors to the ADS8342.
The analog inputs to the ADC consists of two input pins:
AINx and COMMON. The positive input to the ADC, AINx,
is one of four analog channels (AIN0 to AIN3) and is
selected by the front-end multiplexer. When a conversion
is initiated, the differential input on these pins is sampled
on to the internal capacitor array. While a conversion is in
progress, both inputs are disconnected from any internal
function.
MULTIPLEXER
The ADS8342 has an input multiplexer (MUX) that is used
to select the desired positive analog input, and connect the
sample-and-hold circuit and ADC to it. MUX address pins
A0 and A1 are decoded to select the MUX channel; Table 1
shows information on selecting the input channel. Both the
AINx and COMMON input signal voltages are sampled
and held simultaneously to provide the best possible noise
rejection.
Figure 21 shows a block diagram of the input multiplexer
on the ADS8342. The differential input of the converter is
derived from one of the four inputs in reference to the
COMMON pin. Table 1 shows the relationship between
the A1 and A0 control bits and the selection of the analog
multiplexer. The control bits are provided via input pins;
see the Digital Interface section of this data sheet for more
details.
Figure 21. Simplified Diagram of the Analog Input
Table 1. Input Channel Selection
A1
A0
AIN0
AIN1
AIN2
AIN3
COMMON
0
+IN
—
–IN
0
1
—
+IN
—
–IN
1
0
—
+IN
—
–IN
1
—
+IN
–IN
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (Figure 21) is
captured on the internal capacitor array.
SAMPLE-AND-HOLD CIRCUIT
The sample-and-hold circuit on the ADS8342 allows the
ADC to accurately convert an input sine wave of full-scale
amplitude to 16-bit accuracy. The input bandwidth of the
sample-and-hold circuit is greater than the Nyquist rate
(Nyquist equals one-half of the sampling rate) of the ADC
even when the ADC is operated at its maximum
throughput rate of 250kHz.
Typical aperture delay time, or the time it takes for the
ADS8342 to switch from sample mode to hold mode
following the start of conversion, is 8ns. The average delta
of repeated aperture delay values (also known as aperture
jitter) is typically 50ps. These specifications reflect the
ability of the ADS8342 to capture AC input signals
accurately.
ANALOG INPUT
The
analog
input
of
ADS8342
is
bipolar
and
pseudo-differential, as shown in Figure 22. The AIN0 to
AIN3 and COMMON input pins allow for a differential input
signal. The amplitude of the input is the difference between
the AINx and COMMON inputs, or AINx – COMMON.
Unlike some converters of this type, the COMMON input
is not resampled later in the conversion cycle. When the
converter goes into hold mode, the voltage difference
between AINx and COMMON is captured on the internal
capacitor array.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS8342IPFB 制造商:Texas Instruments 功能描述:
ADS8342IPFBR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8342IPFBRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8342IPFBT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8342IPFBTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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