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參數(shù)資料
| 型號： | ADS8342IBPFBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 1129K |
| 代理商： | ADS8342IBPFBTG4 |
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ADS8342
SBAS277 – MAY 2003
www.ti.com
19
START OF A CONVERSION (CS AND CONV)
CS and CONV are NORed together internally and must
both be low to start a conversion. Bringing both the CS and
CONV signals low for 40ns will start a conversion.
Immediately after a conversion is started, the analog
inputs, the selected MUX channel input, and the
COMMON input are held by the sample–and–hold circuit
(8ns).
The conversion starts on the next rising edge of the clock
signal following the conversion start signal, if the
conversion is started at least 40ns before the rising edge
of the next clock (see Figure 2, tD1). The CONV
signal—and CS if it is not always held low—needs to go
high 80ns before the rising edge of the second clock cycle
of the conversion in order to reduce noise caused by bus
activity on the control interface, which can disturb critical
comparator decisions made during the conversion. Once
CONV goes high, it has to stay high during the entire
conversion period (see Figure 2).
After a conversion has been started, the rising edge of
either CS or CONV, whichever is first, latches the MUX
address on pins A0 and A1 in a register. This address is
used to select the channel that will be converted upon the
next conversion start. After a conversion is finished (17
clock cycles), the sample-and-hold circuit switches from
hold mode to sample mode in order to sample the MUX
channel address that was latched during the previous
conversion start. The start of the next conversion can be
initiated after the input capacitor of the ADS8342 is fully
charged. This signal acquisition time depends on the
driving amplifier, but should be at least 600ns.
For best performance, none of the input control lines
should change state after 80ns prior to the rising edge of
the second clock in the conversion, as previously
described.
READING DATA (RD, CS)—CS and RD are NORed
together internally and both must be low to enable the data
outputs. During the conversion, the data outputs are tri-state
and cannot be read. After a conversion has completed, both
CS and RD must be low for at least 40ns (see Figure 2, tW5)
to enable the outputs. The output data can be latched into
external registers using the rising edge of RD and another
conversion can be started 1.5 clocks following the rising edge
of RD. Before bringing RD back low for a subsequent read
command, it must remain high for at least 40ns (see Figure 2,
tW6)
When BUSY rises after a conversion is initiated, the data
outputs will become tri-state regardless of the state of RD.
Noise will be generated when the enabled outputs
transition to tri–state, which can affect the results of the
conversion.
To
obtain
best
performance,
it
is
recommended to read the output data immediately after
the BUSY signal goes low at the end of conversion and to
bring RD high prior to starting the next conversion.
DATA FORMAT
The output data from the ADS8342 is in binary two’s
represents the ideal output code for a given input voltage and
does not include the effects of offset, gain error, or noise.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8342IPFB | 制造商:Texas Instruments 功能描述: |
| ADS8342IPFBR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8342IPFBRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8342IPFBT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8342IPFBTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 250 kSPS Par. Out 4 true bi ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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