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參數資料
| 型號： | ADP5589ACPZ-02-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 41/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC KEY DECODER 19I/O EXP 24LFCSP |
| 標準包裝： | 1,500 |
| 應用： | 小鍵盤輸入，輸入/輸出擴展 |
| 接口： | I²C |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 封裝/外殼： | 24-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-WQ（3.5x3.5） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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ADP5589
Data Sheet
Rev. B | Page 46 of 52
PIN_CONFIG_D Register 0x4C
Table 84. PIN_CONFIG_D Bit Descriptions
Bits
Name
R/W
Description
7
PULL_SELECT
R/W
0 = 300 k used for row pull-up during key scanning.
1 = 100 k used for row pull-up during key scanning.
6
C4_EXTEND_CFG
R/W
0 = C4 remains configured as GPIO 13.
1 = C4 reconfigured as RESET2 output.
5
R4_EXTEND_CFG
R/W
0 = R4 remains configured as GPIO 5.
1 = R4 reconfigured as RESET1 output.
4
C6_EXTEND_CFG
R/W
0 = C6 remains configured as GPIO 15.
1 = C6 reconfigured as LC2 input for Logic Block 2.
[3:2]
R3_EXTEND_CFG[1:0]
R/W
00 = R3 remains configured as GPIO 4.
01 = R3 reconfigured as LC1 input for Logic Block 1.
10 = R3 reconfigured as PWM_OUT/CLK_OUT outputs from PWM and clock divider blocks.
11 = unused.
1
C9_EXTEND_CFG
R/W
0 = C9 remains configured as GPIO 18.
1 = C9 reconfigured as LY2 output from Logic Block 2.
0
R0_EXTEND_CFG
R/W
0 = R0 remains configured as GPIO 1.
1 = R0 reconfigured as LY1 output from Logic Block 1.
ADP5589AC_Z-00-R7, ADP5589AC_Z-02-R7 Default = 0000 0000
ADP5589AC_Z-01-R7 Default = 0010 0000
GENERAL_CFG_B Register 0x4D
Table 85. GENERAL_CFG_B Bit Descriptions
Bits
Name
R/W
Description
7
OSC_EN
R/W
0 = disable internal 1 MHz oscillator.
1 = enable internal 1 MHz oscillator.
[6:5]
CORE_FREQ[1:0]
R/W
Sets the input clock frequency fed from the base 1 MHz oscillator to the digital core. Slower
frequencies result in less IDD. However, key and GPI scan times increase.
00 = 50 kHz.
01 = 100 kHz.
10 = 200 kHz.
11 = 500 kHz.
4
LCK_TRK_LOGIC
R/W
0 = allow logic outputs (programmed for FIFO updates) to be tracked on the FIFO if the keypad is
locked.
1 = do not track.
3
LCK_TRK_GPI
R/W
0 = allow GPIs (programmed for FIFO updates) to be tracked on the FIFO if the keypad is locked.
1 = do not track.
2
Unused
1
INT_CFG
R/W
Configure the behavior of the INT pin if the user tries to clear it while an interrupt is pending.
0 = INT pin remains asserted if an interrupt is pending.
1 = INT pin deasserts for 50 s and reasserts if an interrupt is pending.
0
RST_CFG
R/W
Configure the response ADP5589 has to the RST pin.
0 = ADP5589 resets if RST is low.
1 = ADP5589 does not reset if RST is low.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP5589CP-EVALZ | 功能描述:BOARD EVAL ADP5589ACPZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| ADP-5DB | 制造商:Delta Power 功能描述: |
| ADP-5DB-A | 制造商:Delta Electronics Inc 功能描述: |
| ADP-5DBAB | 制造商:Delta Electronics Inc 功能描述: |
| ADP-5JB-A | 制造商:Delta Electronics Inc 功能描述: |
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