參數(shù)資料
型號(hào)： ADN2855ACPZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 0K
描述： IC CLK/RECOVERY MULTI 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR）
PLL： 是
主要目的： GPON，BPON，GEPON
輸入： CML
輸出： LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 200MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
ADN2855
Rev. A | Page 13 of 20
user exceeds the highest subaddress while reading back in
autoincrement mode, then the highest subaddress register
contents continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. In a no-
acknowledge condition, the SDATA line is not pulled low on the
ninth pulse. See Figure 11 and Figure 12 for sample write and
read data transfers and Figure 13 for a more detailed timing
diagram.
REFERENCE CLOCK
A reference clock is required to perform burst mode clock and
data recovery with the ADN2855. The reference clock must be
frequency locked to the incoming burst data. It is assumed that
the incoming burst data from the ONT is timed by a clock recov-
ered from the downstream data from the OLT and, therefore,
is inherently frequency clocked to the OLT system clock. The
reference clock can be driven differentially or single-ended. See
Figure 15 and Figure 16 for sample configurations.
The REFCLK input buffer accepts any differential signal with
a peak-to-peak differential amplitude of greater than 100 mV
(for example, LVPECL or LVDS) or a standard single-ended
low voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not critical.
06660-
013
REFCLKP
REFCLKN
100kΩ
BUFFER
VCC/2
11
10
Figure 15. Differential REFCLK Configuration
06660-
014
REFCLKP
REFCLKN
100kΩ
BUFFER
VCC/2
OUT
VCC
OSC
CLK
11
10
Figure 16. Single-Ended REFCLK Configuration
The ADN2855 must be operated in lock to reference clock
mode when in burst data recovery mode. Lock to reference
clock mode is enabled by writing a 1 to I2C Control Register
CTRLA, Bit 0. A frequency acquisition in this mode must be
initiated by writing a 1 to 0 transition to CTRLB[5].
Using the Reference Clock to Lock onto Data
In this mode, the ADN2855 locks onto a frequency derived
from the reference clock according to the following equation:
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]
The user must know exactly what the data rate is and provide
a reference clock that is a function of this rate. The reference
clock can be anywhere between 10 MHz and 200 MHz. By
default, the ADN2855 expects a reference clock of between
10 MHz and 25 MHz. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2855 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6].
Table 12. CTRLA Settings
Bit No.
Description
CTRLA[7:6]
FREF range
00 = 10 MHz to 25 MHz
01 = 25 MHz to 50 MHz
10 = 50 MHz to 100 MHz
11 = 100 MHz to 200 MHz
CTRLA[5:2]
Data rate/DIV_FREF ratio
0000 = 1
0001 = 2
…
n = 2n
…
1000 = 256
The user can specify a fixed integer multiple of the reference clock
to lock onto using CTRLA[5:2], where CTRLA should be set to
the data rate/DIV_FREF ratio, where DIV_FREF represents the
divided-down reference referred to the 10 MHz to 25 MHz band.
For example, if the reference clock frequency is 38.88 MHz and
the input data rate is 622.08 Mbps, then CTRLA[7:6] should be
set to 01 to give a divided-down reference clock of 19.44 MHz.
CTRLA[5:2] should be set to 0101, that is, 5, because
622.08 Mbps/19.44 MHz = 25
While the ADN2855 is operating in lock to reference clock mode,
if the user ever changes the reference frequency, the FREF range
(CTRLA[7:6]), or the data rate/DIV_FREF ratio (CTRLA[5:2]),
this must be followed by writing a 0 to 1 transition into the
CTRLB[5] bit to initiate a new frequency acquisition.
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