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參數(shù)資料
| 型號(hào)： | ADN2855ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/RECOVERY MULTI 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | GPON，BPON，GEPON |
| 輸入： | CML |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADN2855
Rev. A | Page 11 of 20
THEORY OF OPERATION
The ADN2855 is designed specifically for burst mode data
recovery in GPON/BPON/GEPON optical line terminal (OLT)
receivers.
The ADN2855 requires a reference clock that is frequency locked
to the incoming data. The FLL (frequency-locked loop) of the
ADN2855 acquires frequency lock with respect to this reference
clock, pulling the VCO towards 0 ppm frequency error. It is
assumed that the upstream bursts to the OLT are clocked by the
recovered clock from the optical network terminal (ONT) CDR.
This guarantees frequency lock to the OLT system clock.
The ADN2855 has a preamble detector that looks for a maximum
transition density pattern (1010…) within the preamble. Once
this pattern is detected in the preamble, the on-chip delay/phase-
locked loop (D/PLL) quickly acquires phase lock to the incoming
burst within 12 UI of the 1010… pattern. The D/PLL also pulls
in any remaining frequency error that was not pulled in by the
FLL. The incoming data is retimed by the recovered clock and
output either serially or in a 4-bit parallel output nibble.
The ADN2855 requires a RESET signal between bursts to set
the device into a fast phase acquisition mode. The RESET signal
must be asserted within 8 UI of the end of the previous burst,
and it must be deasserted prior to the start of the maximum
transition density portion of the preamble, which is specifically
provided for the burst mode clock recovery device to acquire
the phase of the incoming burst. The RESET signal must be at
least 16 UI wide. See the Reset Timing Options section for more
details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2855XCPZ | 功能描述:IC CLK DATA REC GPON 200MHZ 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購(gòu)買時(shí)間 PLL:是 主要用途:GPON，BPON，GEPON 輸入:CML 輸出:LVDS 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:是/是 頻率 - 最大值:200MHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADN2860 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3-Channel Digital Potentiometer with Nonvolatile Memory |
| ADN2860ACPZ25 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADN2860ACPZ250 | 制造商:Analog Devices 功能描述: |
| ADN2860ACPZ250-RL7 | 功能描述:IC POT DGTL 3CH 250K 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲(chǔ)器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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