參數(shù)資料
型號(hào)： ADN2812ACP
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字傳輸電路
英文描述： Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
中文描述： CLOCK RECOVERY CIRCUIT, QCC32
封裝： 5 X 5 MM, MO-220VHHD-2, LFCSP-32
文件頁(yè)數(shù)： 18/28頁(yè)
文件大?。?/td> 478K
代理商： ADN2812ACP
ADN2812
I
2
C INTERFACE
The ADN2812 supports a 2-wire, I
2
C compatible, serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The ADN2812 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave address bits [4:0] are
defaulted to all 0s. The slave address consists of the 7 MSBs of
an 8-bit word. The LSB of the word sets either a read or write
operation (see Figure 7). Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation.
Rev. 0 | Page 18 of 28
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, defined by a high to low transition on SDA
while SCK remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at this
point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines waiting for
the start condition and correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADN2812 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses
plus the R/W bit. The ADN2812 has 8 subaddresses to enable
the user-accessible internal registers (see Table 1 through
Table 7). It, therefore, interprets the first byte as the device
address and the second byte as the starting subaddress.
Autoincrement mode is supported, allowing data to be read
from or written to the starting subaddress and each subsequent
address without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then they cause an
immediate jump to the idle condition. During a given SCK high
period, the user should issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADN2812 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while
reading back in autoincrement mode, then the highest subad-
dress register contents continue to be output until the master
device issues a no-acknowledge. This indicates the end of a read.
In a no-acknowledge condition, the SDATA line is not pulled
low on the ninth pulse. See Figure 8 and Figure 9 for sample
read and write data transfers and Figure 10 for a more detailed
timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2812. However, support for an optional
reference clock is provided. The reference clock can be driven
differentially or single-ended. If the reference clock is not being
used, then REFCLKP should be tied to VCC, and REFCLKN
can be left floating or tied to VEE (the inputs are internally
terminated to VCC/2). See Figure 21 through Figure 23 for
sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility. Phase
noise and duty cycle of the reference clock are not critical and
100 ppm accuracy is sufficient.
0
100k
VCC/2
100k
ADN2812
REFCLKP
10
11
REFCLKN
BUFFER
Figure 21. Differential REFCLK Configuration
0
100k
VCC/2
100k
ADN2812
REFCLKP
OUT
REFCLKN
BUFFER
VCC
CLK
OSC
Figure 22. Single-Ended REFCLK Configuration
0
100k
VCC/2
100k
ADN2812
REFCLKP
10
11
NC
REFCLKN
BUFFER
VCC
Figure 23. No REFCLK Configuration
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADN2812ACP-RL 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R
ADN2812ACP-RL7 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R
ADN2812ACPZ 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
ADN2812ACPZ-RL 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
ADN2812ACPZ-RL7 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
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