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參數(shù)資料
| 型號： | ADN2812ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 478K |
| 代理商： | ADN2812ACP |
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ADN2812
within 250 ppm frequency error. This hysteresis is shown in
Figure 20.
Rev. 0 | Page 17 of 28
0
LOL
0
–250
250
1000
f
ERROR
(ppm)
–1000
1
Figure 20. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In this mode, a reference clock is used as an acquisition aid to
lock the ADN2812 VCO. Lock to reference mode is enabled by
setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits in order to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss of lock signal, which appears on the LOL Pin 16, is de-
asserted when the VCO is within 250 ppm of the desired
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and also acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss of lock signal
is re-asserted and control returns to the frequency loop, which
re-acquires with respect to the reference clock. The LOL pin
remains asserted until the VCO frequency is within 250 ppm of
the desired frequency. This hysteresis is shown in Figure 20.
Static LOL Mode
The ADN2812 implements a static LOL feature, which indicates
if a loss of lock condition has ever occurred and remains
asserted, even if the ADN2812 regains lock, until the static LOL
bit is manually reset. The I
2
C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss of lock
condition, this bit is internally asserted to logic high. The
MISC[4] bit remains high even after the ADN2812 has re-
acquired lock to a new data rate. This bit can be reset by writing
a 1 followed by 0 to I
2
C Register Bit CTRLB[6]. Once reset, the
MISC[4] bit remains de-asserted until another loss of lock
condition occurs.
Writing a 1 to I
2
C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The
CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates
in the normal operating mode, that is, it is asserted only when
the ADN2812 is in acquisition mode and de-asserts when the
ADN2812 has re-acquired lock.
HARMONIC DETECTOR
The ADN2812 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data
instantaneously
changes from OC-48,
2.488 Gb/s, to an OC-12, 622.080 Mb/s bit stream, this could be
perceived as a valid OC-48 bit stream, because the OC-12 data
pattern is exactly 4× slower than the OC-48 pattern. So, if the
change in data rate is instantaneous, a 101 pattern at OC-12
would be perceived by the ADN2812 as a 111100001111 pattern
at OC-48. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2812 implements a harmonic detector that automati-
cally identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2812 automatically locks onto the new data rate, and the
LOL pin is de-asserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate the VCO is currently locked
onto, the VCO loses lock, the LOL pin is asserted, and a new
frequency acquisition is initiated. The ADN2812 automatically
locks onto the new data rate.
The time to detect lock to harmonic is
16,384 × (
T
d
/ρ)
where:
1/
T
d
is the new data rate. For example, if the data rate is
switched from OC-48 to OC-12, then
T
d
= 1/622 MHz.
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2812 is placed in lock to reference mode, the
harmonic detector is disabled.
SQUELCH MODE
Two squelch modes are available with the ADN2812. Squelch
DATAOUT
AND
CLKOUT mode is selected when CTRLC[1] =
0 (default mode). In this mode, when the squelch input, Pin 27,
is driven to a TTL high state, both the clock and data outputs
are set to the zero state to suppress downstream processing. If
the squelch function is not required, Pin 27 should be tied to
VEE.
Squelch DATAOUT
OR
CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the squelch input is driven
to a high state, the DATAOUT pins are squelched. When the
squelch input is driven to a low state, the CLKOUT pins are
squelched. This is especially useful in repeater applications,
where the recovered clock may not be needed.
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