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| 型號(hào)： | ADN2812ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LFCSP-32 |
| 文件頁(yè)數(shù)： | 11/28頁(yè) |
| 文件大小： | 478K |
| 代理商： | ADN2812ACP |
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ADN2812
Table 6. Internal Register Map
1
Reg Name
FREQ0
FREQ1
FREQ2
RATE
Rev. 0 | Page 11 of 28
R/W
R
R
R
R
Address
0x0
0x1
0x2
0x3
D7
MSB
MSB
0
COARSE_RD[8] MSB
D6
MSB
D5
D4
D3
D2
D1
D0
LSB
LSB
LSB
Coarse datarate readback
COARSE_RD[1]
MISC
R
0x4
x
x
LOS
status
Static
LOL
LOL
status
Datarate
measure
complete
x
COARSE_
RD[0] LSB
CTRLA
W
0x8
F
REF
range
Datarate/DIV_F
REF
ratio
Measure
datarate
Lock to
reference
CTRLB
W
0x9
Config
LOL
Reset
MISC[4]
System
reset
0
Reset
MISC[2]
0
0
0
CTRLC
W
0x11
0
0
0
0
0
Config LOS
Squelch
mode
0
1
All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
D7
x
D6
x
LOS Status
D5
0 = No loss of signal
1 = Loss of signal
Static LOL
D4
0 = Waiting for next LOL
1 = Static LOL until reset
LOL Status
D3
0 = Locked
1 = Acquiring
Datarate Measurement
Complete
D2
0 = Measuring datarate
1 = Measurement complete
D1
x
Coarse Rate
Readback LSB
D0
COARSE_RD[0]
Table 8. Control Register, CTRLA
1
F
REF
Range
D7
D6
0
0
12.3 MHz to 25 MHz
0
1
25 MHz to 50 MHz
1
0
50 MHz to 100 MHz
1
1
100 MHz to 200 MHz
1
Where DIV_F
REF
is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
D7
D6
0 = LOL pin normal operation
1 = LOL pin is static LOL
0 to reset MISC[4]
Datarate/Div_F
REF
Ratio
D5
D4
0
0
0
0
0
0
n
1
0
Measure Datarate
D1
Set to 1 to measure datarate
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
D3
0
0
1
D2
0
1
0
1
2
4
2
n
256
0
0
System Reset
D5
Write a 1 followed by
0 to reset ADN2812
D4
Set
to 0
Reset MISC[2]
D3
Write a 1 followed by
0 to reset MISC[2]
D2
Set
to 0
D1
Set
to 0
D0
Set
to 0
Write a 1 followed by
Table 10. Control Register, CTRLC
D7
D6
Set to 0
Set to 0
D5
Set to 0
D4
Set to 0
D3
Set to 0
Config LOS
D2
0 = Active high LOS
1 = Active low LOS
Squelch Mode
D1
0 = Squelch CLK and DATA
1 = Squelch CLK or DATA
D0
Set to 0
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| ADN2812ACPZ | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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