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參數(shù)資料
| 型號(hào)： | ADN2812ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 478K |
| 代理商： | ADN2812ACP |
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ADN2812
TERMINOLOGY
Input Sensitivity and Input Overdrive
Rev. 0 | Page 12 of 28
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 12. For sufficiently large positive input voltage,
the output is always Logic 1 and, similarly for negative inputs,
the output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels, but occur over a range of input voltages. Within
this range of input voltages, the output might be either 1 or 0, or
it might even fail to attain a valid logic state. The width of this
zone is determined by the input voltage noise of the quantizer.
The center of the zone is the quantizer input offset voltage.
Input overdrive is the magnitude of signal required to guarantee
the correct logic level with 1 × 10
10
confidence level.
0
NOISE
OUTPUT
INPUT (V p-p)
OFFSET
OVERDRIVE
SENSITIVITY
(2
×
OVERDRIVE)
1
0
Figure 12. Input Sensitivity and Input Overdrive
Single-Ended vs. Differential
AC coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a common-
mode potential of ~2.5 V. Driving the ADN2812 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 13 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values both above and below the average value. It
is convenient to measure the peak-to-peak amplitude of this
signal and call the minimum required value the quantizer
sensitivity. Referring to Figure 13, because both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive. The ADN2812 quantizer typically has
6 mV p-p sensitivity.
0
SCOPE
PROBE
PIN
50
3k
2.5V
50
VREF
ADN2812
QUANTIZER
+
–
10mV p-p
VREF
Figure 13. Single-Ended Sensitivity Measurement
Driving the ADN2812 differentially (see Figure 14), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2812 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value, because the other quantizer input is a complementary
signal to the signal being observed.
0
SCOPE
PROBE
PIN
50
3k
2.5V
50
VREF
QUANTIZER
+
–
NIN
5mV p-p
VREF
5mV p-p
VREF
Figure 14. Differential Sensitivity Measurement
LOS Response Time
LOS response time is the delay between removal of the input
signal and indication of loss of signal (LOS) at the LOS output,
Pin 22. When the inputs are dc-coupled, the LOS assert time of
the AD2812 is 500 ns typically and the de-assert time is 400 ns
typically,. In practice, the time constant produced by the ac
coupling at the quantizer input and the 50 on-chip input
termination determines the LOS response time.
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| ADN2812ACP-RL | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2812ACP-RL | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACP-RL7 | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACPZ | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ADN2812ACPZ-RL | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2812ACPZ-RL7 | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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