Timing Requirements: t IFS IRQx or FI Setup before CLKOUT Low
參數(shù)資料
型號: ADMC401BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 56/60頁
文件大?。?/td> 0K
描述: IC DSP 8CH 12BIT MOTCTRL 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: 電機(jī)控制
類型: 定點(diǎn)
接口: 串行端口
時鐘速率: 26MHz
非易失內(nèi)存: ROM(6 kB)
芯片上RAM: 8kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
REV. B
ADMC401
–6–
Parameter
Min
Max
Unit
Interrupts and Flags
Timing Requirements:
t
IFS
IRQx or FI Setup before CLKOUT Low1, 2, 3
0.25t
CK + 15
ns
t
IFH
IRQx or FI Hold after CLKOUT High1, 2, 3
0.25t
CK
ns
Switching Characteristics:
t
FOH
Flag Output Hold after CLKOUT Low
4
0.5t
CK – 7
ns
t
FOD
Flag Output Delay from CLKOUT Low
4
0.5t
CK + 5
ns
NOTES
1If
IRQx and FI inputs meet t
IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition for further
information on interrupt servicing.)
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0 and IRQ1.
4Flag Output = FL1 and FO.
CLKOUT
FLAG
OUTPUTS
IRQx
FI
tFOH
tIFH
tIFS
tFOD
Figure 2. Interrupts and Flags
相關(guān)PDF資料
PDF描述
ADN2850BCPZ25-RL7 IC DGTL RHEO DL 25K 9BIT16LFCSP
ADN2860ACPZ250-RL7 IC POT DGTL 3CH 250K 24-LFCSP
ADN4600ACPZ IC CROSSPOINT SWITCH 8X8 64LFCSP
ADN4604ASVZ-RL IC CROSSPOINT SWIT 16X16 100TQFP
ADN4605ABPZ IC CROSSPOINT SWITCH 352BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADMC401BSTZKL1 制造商:Analog Devices 功能描述:
ADMC401-PB 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Chip, DSP-Based High Performance Motor Controller
ADMCF326 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead Flash Memory DSP Motor Controller
ADMCF326BN 制造商:Analog Devices 功能描述:
ADMCF326BR 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead Flash Memory DSP Motor Controller