參數(shù)資料
型號： ADMC401BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/60頁
文件大?。?/td> 0K
描述： IC DSP 8CH 12BIT MOTCTRL 144LQFP
標(biāo)準(zhǔn)包裝： 1
系列： 電機(jī)控制
類型： 定點(diǎn)
接口： 串行端口
時(shí)鐘速率： 26MHz
非易失內(nèi)存： ROM（6 kB）
芯片上RAM： 8kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
REV. B
ADMC401
–30–
cycle of the signals on CH and CL. The duty cycle registers are
programmed in integer counts of the fundamental time unit,
tCK, and define the desired on-time of the high side PWM signal
produced by the three-phase timing unit over half the PWM pe-
riod. The switching signals produced by the three-phase timing
unit are also adjusted to incorporate the programmed dead time
value in the PWMDT register. The three-phase timing unit
produces active LO signals so that a LO level corresponds to a
command to turn on the associated power device.
A typical pair of PWM outputs (in this case for AH and AL)
from the timing unit are shown in Figure 22 for operation in
single update mode. All illustrated time values indicate the
integer value in the associated register and can be converted to
time by simply multiplying by the fundamental time increment,
tCK. First, it is noted that the switching patterns are symmetrical
about the midpoint of the switching period in this single up-
date mode since the same values of PWMCHA, PWMTM and
PWMDT are used to define the signals in both half cycles of the
period. It can be seen how the programmed duty cycles are
adjusted to incorporate the desired dead time into the resultant
pair of PWM signals. Clearly, the dead time is incorporated by
moving the switching instants of both PWM signals (AH and
AL) away from the instant set by the PWMCHA register. Both
switching edges are moved by an equal amount (PWMDT
×
tCK) to preserve the symmetrical output patterns. Also shown is
the PWMSYNC pulse whose width is set by the PWMSYNCWT
register and Bit 3 of the SYSSTAT register, which indicates
whether operation is in the first or second half cycle of the PWM
period.
PWMSYNC
AH
AL
PWMCHA
2
PWMDT
PWMSYNCWT + 1
2
PWMDT
SYSSTAT (3)
PWMTM
Figure 22. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode (Active LO Waveforms)
The resultant on-times of the PWM signals over the full PWM
period (two half periods) produced by the PWM timing unit,
and illustrated in Figure 22, may be written as:
T
PWMCHA PWMDT
t
AH
CK
=×
()×
2–
T
PWMTM
PWMCHA PWMDT
t
AL
CK
=×
()×
2–
–
and the corresponding duty cycles are:
d
T
PWMCHA PWMDT
PWMTM
AH
S
==
–
d
T
PWMTM
PWMCHA PWMDT
PWMTM
AL
S
==
––
Obviously negative values of TAH and TAL are not permitted and
the minimum permissible value is zero, corresponding to a 0%
duty cycle. In a similar fashion, the maximum value is TS, corre-
sponding to a 100% duty cycle.
The output signals from the timing unit for operation in double
update mode are shown in Figure 23. This illustrates a com-
pletely general case where the switching frequency, dead time
and duty cycle are all changed in the second half of the PWM
period. Of course, the same value for any or all of these quanti-
ties could be used in both halves of the PWM cycle. However, it
can be seen that there is no guarantee that symmetrical PWM
signals will be produced by the timing unit in this double update
mode. Additionally, it is seen that the dead time is inserted into
the PWM signals in the same way as in the single update mode.
PWMCHA2
2
PWMDT1
2
PWMDT2
PWMSYNCWT2 + 1
PWMCHA1
PWMTM1
PWMTM2
PWMSYNCWT1 + 1
AH
AL
PWMSYNC
SYSSTAT (3)
Figure 23. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode (Active LO Waveforms)
In general the on-times of the PWM signals over the full PWM
period in double update mode can be defined as:
T
PWMCHA
PWMDT
t
AH
CK
=+
() ×
12
1
2
––
T
PWMTM
PWMCHA
PWMDT
t
AL
CK
=+
(
) ×
12
1
2
1
2
––
–
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
d
T
PWMCHA
PWMDT
PWMTM
AH
S
==
+
12
1
2
12
––
d
T
PWMTM
PWMCHA
PWMDT
PWMTM
AL
S
==
++
+
1
212
1
2
12
––
–
since for the completely general case in double update mode,
the switching period is given by:
T
PWMTM
t
SCK
=+
() ×
12
Again, the values of TAH and TAL are constrained to lie between
zero and TS. Similar PWM signals to those illustrated in Figure
22 and Figure 23 can be produced on the BH, BL, CH and CL
outputs by programming the PWMCHB and PWMCHC registers
in a manner identical to that described for PWMCHA.
Special Consideration for PWM Operation in
Overmodulation
The PWM Timing Unit is capable of producing PWM signals
with variable duty cycle values at the PWM output pins. At the
extremities of the modulation process, both 0% and 100%
modulation are possible. These two modes are termed full OFF
and full ON respectively. In between, for other duty cycle val-
ues, the operation is termed normal modulation.
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