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參數(shù)資料
| 型號： | ADMC401BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/60頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 8CH 12BIT MOTCTRL 144LQFP |
| 標準包裝： | 1 |
| 系列： | 電機控制 |
| 類型： | 定點 |
| 接口： | 串行端口 |
| 時鐘速率： | 26MHz |
| 非易失內(nèi)存： | ROM（6 kB） |
| 芯片上RAM： | 8kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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ADMC401
–19–
REV. B
SYSTEM INTERFACE
CLOCK SIGNALS
The ADMC401 uses an input clock with a frequency equal to
half the instruction rate; a 13 MHz input clock yields a 38.5 ns
processor cycle (which is equivalent to 26 MHz). Normally
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction rate, which is indi-
cated by the CLKOUT signal (when enabled). Throughout this
data sheet, the period of the CLKIN signal is denoted by tCKI.
The DSP instruction period is tCK (the period of the CLKOUT
signal), and tCK = 0.5
× t
CKI. For 26 MIPS operation, a 13 MHz
CLKIN signal is used, corresponding to tCKI = 76.9 ns and tCK
= 38.5 ns. Additionally, tCK is the fundamental time increment
of the motor control peripherals. Therefore, unless otherwise
specified, the motor control peripherals are clocked at a rate
equal to CLKOUT. The ADMC401 can be clocked by either a
crystal or by an external clock source. The CLKIN input cannot
be halted, changed in frequency, or operated below the specified
minimum frequency during normal operation.
If an external clock source is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the CLKIN pin of the ADMC401. In this mode, with
an external clock signal, the XTAL pin must be left unconnected.
Because the ADMC401 includes an on-chip oscillator circuit,
an external crystal may be used instead of a clock source. The
crystal should be connected across the CLKIN and XTAL pins.
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal should be used. The frequency value selected for
the crystal should be equal to half the desired instruction rate
for the processor. Figure 15 shows a 13 MHz crystal properly
connected to yield a 26 MHz processor rate.
The CLKOUT output can be enabled and disabled by the
CLKODIS bit of the SPORT0 Autobuffer Control Register,
DM (0x3FF3). However, extreme care must be exercised when
using this bit (and is thus discouraged) since disabling CLKOUT
effectively disables all motor control peripherals, except the
watchdog timer.
RESET AND POWER-ON RESET CIRCUIT
The
RESET pin initiates a complete hardware reset of the
ADMC401 when pulled low. The
RESET signal must be asserted
when the device is powered up to assure proper initialization.
The ADMC401 contains an integrated power-on reset circuit
that provides an output reset signal,
POR, from the ADMC401
on power up and if the power supply voltage falls below the
threshold level. The ADMC401 may be reset from an external
source using the
RESET signal or alternatively the internal
power-on reset circuit may be used by connecting the
POR pin
to the
RESET pin. During power-up the RESET line must be
activated for long enough to allow the DSP core’s internal clock
to stabilize. The power-up sequence is defined as the total time
required for the crystal oscillator to stabilize after a valid VDD is
applied to the processor and for the internal phase locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000tCKI cycles will ensure that the PLL has locked (this does not
include the crystal oscillator start-up time).
The operation of the internal power-on reset circuit is illustrated
in Figure 14. On power-up, the circuit maintains the
POR pin
low until it detects that the VDD line has attained the threshold
voltage, VRST level. As soon as the threshold voltage is attained,
the power on reset circuit enables a 17-bit counter that is
clocked at the CLKOUT rate. While the counter is counting the
POR pin is held low. When the counter overflows, after a time:
tms
RST
=×
×
=
2
38 5
10
2 52
16
9
..
–
the
POR pin is brought high and if the POR and RESET pins
are connected, the device is brought out of reset.
The internal power-on reset circuit also acts as a power supply
monitor and puts the
POR pin at a LO level if it detects a volt-
age less than VRST–VHYST, where VHYST is the hysteresis voltage
built into the POR circuit. The supply voltage must then exceed
VRST to initiate another power-on reset sequence.
VDD
POR
tRST
VRST
VRST - VHYST
Figure 14. Operation of Power-On Reset (POR) Circuit of
ADMC401
The master reset (
RESET = LO) causes a Full System Reset,
which sets all internal stack pointers to the empty stack condi-
tion, masks all interrupts, clears the MSTAT register, restores
the program counter to its initial value and performs a full reset
of all of the motor control peripherals including the watchdog
timer. Following a power-up, it is possible to initiate a Full
System Reset by simply pulling the
RESET low. For these
resets, there is no need to wait for PLL stabilization and the
RESET signal must meet the minimum pulsewidth specifica-
tion, tRSP. To generate the external RESET signal, it is recom-
mended to use either an RC circuit with a Schmitt trigger or a
commercially available reset IC.
Separate from a Full System Reset, a software controlled Periph-
eral Reset (excluding the watchdog timer) is achieved by toggling
the DSP FL2 flag with the following code segment:
PRESET:
SET FL2;
TOGGLE FL2;
RTS;
A full DSP and peripheral reset (except the watchdog timer
itself) will occur automatically on a watchdog trip.
EXTERNAL MEMORY INTERFACE
The ADMC401 can address 14K
× 24 bits of external program
memory and up to 13K
× 16 bits of external data memory. The
ADMC401 provides the address on a 14-bit address bus
(A13–A0). Instructions or data are transferred across the 24-bit
data bus (D23–D0) during program memory accesses. During
data memory accesses, data is transferred on the 16 most signifi-
cant bits (D23–D8) of the data bus. For a dual off-chip fetch,
the data from program memory is read first, then the data from
data memory. The program memory select pin,
PMS, is acti-
vated during external program memory accesses and can be
used as a chip select signal for the external program memory
devices. Similarly, for external data memory accesses, the
DMS
pin is activated.
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