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參數資料
| 型號： | ADM9240ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Low Cost Microprocessor System Hardware Monitor |
| 中文描述： | 9-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數： | 16/22頁 |
| 文件大?。?/td> | 280K |
| 代理商： | ADM9240ARU |
ADM9240
–16–
REV. 0
T he structure of the NAND tree is shown in Figure 13.
Beginning with A1 and working clockwise around the chip, each
pin can be toggled and a resulting toggle can be observed on
NT EST _OUT /A0.
Allow for a typical propagation delay of 500 ns.
SDA
SCL
FAN1
FAN2
VID0
VID1
VID2
VID3
VID4
A1
NTEST_OUT
Figure 13. NAND Tree
Note: If any of the inputs shown in Figure 9 are unused, they
should not be connected directly to ground, but via a resistor
such as 10 k
. T his will allow the AT E (Automatic T est Equip-
ment) to drive every input high so that the NAND tree test can
be properly carried out.
USING T HE ADM9240
POWE R-ON RE SE T
When power is first applied, the ADM9240 performs a “power-
on reset” on several of its registers. Registers whose power-on
values are not shown have power-on conditions that are indeter-
minate (this includes the Value and Limit Registers). T he ADC
is inactive. In most applications, usually the first action after
power-on would be to write limits into the Limit Registers.
Power-on reset clears or initializes the following registers (the
initialized values are shown in T able VI:
– Configuration Register
– Serial Address Register
– Interrupt (INT ) Status Registers #1 and #2
– Interrupt (INT ) Mask Registers #1 and #2
– VID /Fan Divisor Register
– VID4 Register
– Chassis Intrusion Clear Register
– T emperature Configuration Register
– T est Register
– Compatibility Register
– Analog Output Register
INIT IALIZAT ION
Configuration Register INIT IALIZAT ION performs a similar,
but not identical, function to power-on reset. T he T est Register
and Analog Output Register are not initialized.
Configuration Register INIT IALIZAT ION is accomplished by
setting Bit 7 of the Configuration Register high. T his bit auto-
matically clears after being set.
Using the Configuration Register
Control of the ADM9240 is provided through the Configuration
Register. T he ADC is stopped upon power-up, and the
INT
_Clear
signal is asserted, clearing the
INT
output. T he Configuration
Register is used to start and stop the ADM9240; enable or dis-
able interrupt outputs and modes, and provide the initialization
function described above.
Bit 0 of the Configuration Register controls the monitoring loop
of the ADM9240. Setting Bit 0 low stops the monitoring loop
and puts the ADM9240 into a low power mode thereby reduc-
ing power consumption. Serial bus communication is still pos-
sible with any register in the ADM9240 while in low power
mode. Setting Bit 0 high starts the monitoring loop.
Bit 1 of the Configuration Register enables or disables the
INT
Interrupt output. Setting Bit 1 high enables the
INT
output,
setting Bit 1 low disables the output.
Bit 3 of the Configuration Register is used to clear the
INT
interrupt output when set high. T he ADM9240 monitoring
function will stop until Bit 3 is set low. Interrupt Status Register
contents will not be affected.
Bit 4 of the Configuration Register is used to initiate a mini-
mum 20 ms
RESET
signal on the
RESET
output if the function
is enabled by Bit 7 in Register 44.
Bit 6 of the Configuration Register is used to reset the Chassis
Intrusion (CI) output pin when set high.
Bit 7 of the Configuration Register is used to start a Configura-
tion Register Initialization when taken high.
ST ART ING CONVE RSION
T he monitoring function (analog inputs, temperature and fan
speeds) in the ADM9240 is started by writing to the Configura-
tion Register and setting Start (Bit 0), high,
INT
_Enable (Bit 1)
high and
INT
_Clear (Bit 3) low. Apart from initially starting
together, the analog measurements and fan speed measurements
proceed independently and are not synchronized in any way.
T he analog measurements will be completed in no more than
353
μ
s. T he time taken to complete the fan speed measurements
depends on the fan speed and the number of tacho output pulses
per revolution.
Once the measurements have been completed, the results can be
read from the Value Registers at any time.
T able IV shows the measurement sequence for the analog inputs.
T able IV. Measurement Sequence
Measurement #
Parameter
1
2
3
4
5
6
7
Analog +V
CCP2
Analog +12 V
IN
Analog +5 V
IN
Analog +3.3 V
IN
Analog +2.5 V
IN
Analog +V
CCP1
T emperature Reading
LOW POWE R AND SHUT DOWN MODE
T he ADM9240 can be placed in a low power mode by setting
Bit 0 of the Configuration register to 0. T his disables the inter-
nal ADC. Full shutdown mode may then be achieved by setting
Bit 0 of the T est Register to 1. T his turns off the analog output
and stops the monitoring cycle, if running, but it does not affect
the condition of any of the registers. T he device will return to its
previous state when this bit is reset to zero.
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