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參數(shù)資料
| 型號： | ADM9240ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Low Cost Microprocessor System Hardware Monitor |
| 中文描述： | 9-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 280K |
| 代理商： | ADM9240ARU |
ADM9240
–15–
REV. 0
INT E RRUPT CLE ARING
Reading an Interrupt Status Register will output the contents of
the Register, then clear it. It will remain cleared until the moni-
toring cycle updates it, so the next read operation should not be
performed on the register until this has happened, or the result
will be invalid. T he time taken for a complete monitoring cycle
is mainly dependent on the time taken to measure the fan speeds,
as described earlier.
T he
INT
output is cleared with the
INT
_Clear bit, which is Bit
3 of the Configuration Register, without affecting the contents
of the Interrupt (INT ) Status Registers. When this bit is high,
the ADM9240 monitoring loop will stop. It will resume when
the bit is low.
T E MPE RAT URE INT E RRUPT MODE S
As mentioned earlier, two limit values can be programmed for
the temperature measurement, a Hot T emperature Limit (T
HOT
),
and a Hot T emperature Hysteresis Limit (T
HOT HYST
), which is
normally some degrees lower.
T he interrupt function of the temperature sensor differs from
the interrupt operation of the other inputs in that there are three
interrupt modes, called “One-T ime Interrupt” mode, “Default
Interrupt” mode and “Comparator” mode.
DE FAULT INT E RRUPT MODE
Exceeding T
HOT
causes an Interrupt that will remain active
indefinitely until reset by reading Interrupt Status Register 1 or
cleared by the
INT
_Clear bit in the Configuration register.
Once an Interrupt event has occurred by crossing T
HOT
, then
reset, an Interrupt will occur again once the next temperature
conversion has completed. T he interrupts will continue to occur
in this manner until the temperature goes below T
HOT HYST
.
Operation in the default interrupt mode is illustrated in Figure
10. For clarity, in this illustration the interval between read
operations is shown as considerably longer than the monitoring
cycle time, so that the interrupt is always reasserted after being
reset, before the next read operation occurs.
TEMP
READ
READ
READ
READ
READ
READ
READ
INT
T
HOT
T
HOTHYST
Figure 10. Temperature
INT
Output in Default Interrupt
Mode
ONE -T IME INT E RRUPT MODE
Exceeding T
HOT
causes an Interrupt that will remain active
indefinitely until reset by reading Interrupt Status Register 1 or
cleared by the
INT
_Clear bit in the Configuration Register.
Once an Interrupt event has occurred by crossing T
HOT
, then
reset, an Interrupt will not occur again until the temperature
goes below T
HOT HYST
. Operation in the one-time interrupt
mode is illustrated in Figure 11. Again, the interval between
read operations is shown as being longer than the monitoring
cycle time.
READ
READ
READ
READ
READ
READ
READ
INT
T
HOT
T
HOTHYST
TEMP
Figure 11.
INT
Output in One-Time Interrupt Mode
COMPARAT OR MODE
Exceeding T
HOT
causes the
INT
output to go Low.
INT
will
remain Low until the temperature goes below T
HOT
. Once the
temperature goes below T
HOT
,
INT
will go High. T
HOT HYST
is
ignored. In other words, Comparator Mode operates like a
thermostat with no hysteresis. Operation in the comparator
mode is illustrated in Figure 12.
INT
T
HOT
TEMP
Figure 12.
INT
Output in Comparator Mode
RESET
INPUT /OUT PUT
RESET
(Pin 12) is an I/O pin that can function as an open-
drain output, providing a low going 20 ms output pulse when
Bit 4 of the Configuration Register is set to 1, provided the reset
function has first been enabled by setting Bit 7 of Interrupt
Mask Register #2 to 1. T he bit is automatically cleared when
the reset pulse is output. Pin 11 can also function as a
RESET
input by pulling this pin low to reset the internal registers of the
ADM9240 to default values. Only those registers that have
power on default values as listed in T able VI are affected by this
function. T he DAC register, Value and Limit Registers are not
affected.
NAND T RE E T E ST S
A NAND tree is provided in the ADM9240 for Automated T est
Equipment (AT E) board level connectivity testing. T he device
is placed into NAND T est Mode by powering up with Pin 11
held high. T his pin is sampled automatically after power-up and
if it connected high, then the NAND test mode is invoked.
In NAND test mode, all digital inputs may be tested as illus-
trated below. A0/NT EST _OUT will become the NAND tree
output pin. T o perform a NAND tree test, all pins included in
the NAND tree should be driven high.
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