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參數(shù)資料
| 型號： | ADF4151BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
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ADF4151
Data Sheet
Rev. B | Page 22 of 28
FAST LOCK—AN EXAMPLE
If a PLL has a reference frequency of 13 MHz, a fPFD of 13 MHz
and a required lock time of 50 s, the PLL is set to wide bandwidth
for 40 s. This example assumes a modulus of 65 for channel
spacing of 200 kHz.
If the time period set for the wide bandwidth is 40 s, then
Fast Lock Timer Value = Time In Wide Bandwidth × fPFD/MOD
Fast Lock Timer Value = 40 s × 13 MHz/65 = 8
Therefore, 8 must be loaded into the clock divider value in
Register 3 in Step 1 of the sequence described in the Fast Lock
FAST LOCK—LOOP FILTER TOPOLOGY
To use fast lock mode, the damping resistor in the loop filter
is reduced to of its value while in wide bandwidth mode. To
achieve the wider loop filter bandwidth, the charge pump
current increases by a factor of 16. To maintain loop stability,
the damping resistor must be reduced a factor of . To enable
fast lock, the SW pin is shorted to the GND pin by setting
Bits[DB16:DB15] in Register 3 to values 0, 1. The following two
topologies are available:
The damping resistor (R1) is divided into two values (R1
and R1A) that have a ratio of 1:3 (see Figure 26).
An extra resistor (R1A) is connected directly from SW,
as shown in Figure 27. The extra resistor is calculated
such that the parallel combination of an extra resistor
and the damping resistor (R1) is reduced to of the
original value of R1 (see Figure 27).
ADF4151
CPOUT
SW
C1
C2
R2
R1
R1A
C3
VCO
10265-
026
Figure 26. Fast Lock Loop Filter Topology—Topology 1
ADF4151
CPOUT
SW
C1
C2
R2
R1
R1A
C3
VCO
10265-
027
Figure 27. Fast Lock Loop Filter Topology—Topology 2
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4151.
Fractional Spurs
The fractional interpolator in the ADF4151 is a third-order Σ-Δ
modulator (SDM) with a modulus (MOD) that is programmable
to any integer value from 2 to 4095. In low spur mode (dither
enabled), the minimum allowable value of MOD is 50. The
SDM is clocked at the PFD reference rate (fPFD) that allows PLL
output frequencies to be synthesized at a channel step resolution
of fPFD/MOD.
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order modulator
used in the ADF4151, the repeat length depends on the value
of MOD, as listed in Table 7.
Table 7. Fractional Spurs with Dither Off
Condition (Dither Off)
Repeat
Length
Spur Interval
If MOD is divisible by 2, but not 3
2 × MOD
Channel step/2
If MOD is divisible by 3, but not 2
3 × MOD
Channel step/3
If MOD is divisible by 6
6 × MOD
Channel step/6
Otherwise
MOD
Channel step
In low spur mode (dither on), the repeat length is extended to
221 cycles, regardless of the value of MOD, which makes the
quantization error spectrum look like broadband noise. This
may degrade the in-band phase noise at the PLL output by as
much as 10 dB. For lowest noise, dither off is a better choice,
particularly when the final loop bandwidth is low enough to
attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (the point of a
fractional-N synthesizer) spur sidebands appear on the VCO
output spectrum at an offset frequency that corresponds to the
beat note or difference frequency between an integer multiple of
the reference and the VCO frequency. These spurs are attenuated
by the loop filter and are more noticeable on channels close to
integer multiples of the reference where the difference frequency
can be inside the loop bandwidth; therefore, the name integer
boundary spurs.
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| ADF4151BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4152HVBCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4152HVBCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4153 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| ADF4153ABCPZ | 制造商:Analog Devices 功能描述:SINGLE RF F-N PLL 制造商:Analog Devices 功能描述:SINGLE RF F-N PLL - Trays 制造商:Analog Devices 功能描述:IC PLL FREQ SYNTHESIZER 20-LFCSP 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER 4GHZ 20 制造商:Analog Devices 功能描述:IC, FREQ SYNTHESIZER, 4GHZ, 20LFCSP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Single RF F-N PLL 制造商:Analog Devices 功能描述:PLL SYNTHESIZER, FREQUENCY, 4GHZ, LFCSP-20; PLL Type:Frequency Synthesis; Frequency:4GHz; Supply Current:20mA; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Digital IC Case Style:LFCSP; No. of Pins:20; Package / Case:20-LFCSP 制造商:Analog Devices 功能描述:IC, FREQ SYNTHESIZER, 4GHZ, 20LFCSP; Synthesizer Type:Frequency; Frequency:4GHz; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Supply Current:20mA; Digital IC Case Style:LFCSP; No. of Pins:20; Operating Temperature Min:-40C; ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:PLL SYNTHESIZER, FREQUENCY, 4GHZ, LFCSP-20; PLL Type:Frequency Synthesis; Frequency:4GHz; Supply Current:20mA; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Digital IC Case Style:LFCSP; No. of Pins:20; Package / Case:20-LFCSP ;RoHS Compliant: Yes |
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