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參數(shù)資料
| 型號(hào)： | ADF4151BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/28頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
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Data Sheet
ADF4151
Rev. B | Page 21 of 28
A 13 MHz reference signal can be fed directly to the PFD, and
the modulus can be programmed to 520 when in PDC mode
(13 MHz/520 = 25 kHz).
The modulus needs to be reprogrammed to 65 for GSM 1800
operation (13 MHz/65 = 200 kHz).
It is important that the PFD frequency remain constant (13 MHz).
This allows the user to design one loop filter for both setups
without running into stability issues. It is important to remem-
ber that the ratio of the RF frequency to the PFD frequency
principally affects the loop filter design, not the actual channel
spacing.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
As outlined in the Low Noise and Spur Mode section, the
ADF4151 contains a number of features that allow optimization
for noise performance. However, in fast locking applications,
the loop bandwidth generally needs to be wide, and, therefore,
the filter does not provide much attenuation of the spurs. If
the cycle slip reduction feature is enabled, the narrow-loop
bandwidth is maintained for spur attenuation but faster lock
times are still possible.
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when
the loop bandwidth is narrow compared to the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the
PLL to correct, and the charge pump temporarily pumps in the
wrong direction. This slows down the lock time dramatically.
The ADF4151 contains a cycle slip reduction feature that
extends the linear range of the PFD, allowing faster lock
times without modifications to the loop filter circuitry.
When the circuitry detects that a cycle slip is about to occur,
it turns on an extra charge pump current cell. This outputs a
constant current to the loop filter or removes a constant
current from the loop filter (depending on whether the VCO
tuning voltage needs to increase or decrease to acquire the
new frequency). The effect is that the linear range of the PFD
is increased. Loop stability is maintained because the current
is constant and is not a pulsed current.
If the phase error increases again to a point where another cycle
slip is likely, the ADF4151 turns on another charge pump cell.
This continues until the ADF4151 detects that the VCO
frequency has gone past the desired frequency. The extra charge
pump cells are turned off one by one until all the extra charge
pump cells have been disabled and the frequency is settled with
the original loop filter bandwidth.
Up to seven extra charge pump cells can be turned on. In most
applications, it is enough to eliminate cycle slips altogether,
giving much faster lock times.
Setting Bit DB18 in the Register 3 to 1 enables cycle slip
reduction. Note that the PFD requires a 45% to 55% duty
cycle for CSR to operate correctly.
SPURIOUS OPTIMIZATION AND FAST LOCK
Narrow-loop bandwidths can filter unwanted spurious signals,
but these usually have a long lock time. A wider loop bandwidth
achieves faster lock times, but a wider loop bandwidth may lead
to increased spurious signals inside the loop bandwidth.
The fast lock feature can achieve the same fast lock time as the
wider bandwidth, but with the advantage of a narrow final loop
bandwidth to keep spurs low.
FAST LOCK TIMER AND REGISTER SEQUENCES
If the fast lock mode is used, a timer value must be loaded into
the PLL to determine the duration of the wide bandwidth mode.
When Bits[DB16:DB15] in Register 3 are set to 0, 1 (fast
lock enable), the timer value is loaded by the 12-bit clock
divider value. The following sequence must be programmed
to use fast lock:
1. Initialization sequence (see the Initialization Sequence
section); occurs only once after powering up the part.
2. Load Register 3 by setting Bits[DB16:DB15] to 0, 1 and
the chosen fast lock timer value, Bits[DB14:DB3]. Note that
the length of time the PLL remains in wide bandwidth is
equal to the fast lock timer/fPFD.
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參數(shù)描述 |
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| ADF4151BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4152HVBCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4152HVBCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4153 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| ADF4153ABCPZ | 制造商:Analog Devices 功能描述:SINGLE RF F-N PLL 制造商:Analog Devices 功能描述:SINGLE RF F-N PLL - Trays 制造商:Analog Devices 功能描述:IC PLL FREQ SYNTHESIZER 20-LFCSP 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER 4GHZ 20 制造商:Analog Devices 功能描述:IC, FREQ SYNTHESIZER, 4GHZ, 20LFCSP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Single RF F-N PLL 制造商:Analog Devices 功能描述:PLL SYNTHESIZER, FREQUENCY, 4GHZ, LFCSP-20; PLL Type:Frequency Synthesis; Frequency:4GHz; Supply Current:20mA; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Digital IC Case Style:LFCSP; No. of Pins:20; Package / Case:20-LFCSP 制造商:Analog Devices 功能描述:IC, FREQ SYNTHESIZER, 4GHZ, 20LFCSP; Synthesizer Type:Frequency; Frequency:4GHz; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Supply Current:20mA; Digital IC Case Style:LFCSP; No. of Pins:20; Operating Temperature Min:-40C; ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:PLL SYNTHESIZER, FREQUENCY, 4GHZ, LFCSP-20; PLL Type:Frequency Synthesis; Frequency:4GHz; Supply Current:20mA; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Digital IC Case Style:LFCSP; No. of Pins:20; Package / Case:20-LFCSP ;RoHS Compliant: Yes |
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