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參數(shù)資料
| 型號(hào)： | ADF4151BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
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Data Sheet
ADF4151
Rev. B | Page 19 of 28
REGISTER 3
Control Bits
With Bits[C3:C1] set to 0, 1, 1, Register 3 is programmed.
Figure 22 shows the input data format for programming
this register.
Antibacklash Pulse Width
Setting DB22 to 0 sets the PFD antibacklash pulse width to 6 ns.
This is the recommended mode for fractional-N use. By setting
this bit to 1, the 3 ns pulse width is used and results in a phase
noise and spur improvement in integer-N operation. For
fractional-N mode it is not recommended to use this smaller
setting.
Charge Cancellation Mode Pulse Width
Setting DB21 to 1 enables charge pump charge cancellation.
This has the effect of reducing PFD spurs in integer-N mode.
In fractional-N mode, this bit should not be used. This results
in a phase noise and fractional spur improvement.
Cycle Slip Reduction (CSR) Enable
Setting DB18 to 1 enables cycle slip reduction. This is a method
for improving lock times. Note that the signal at the phase fre-
quency detector (PFD) must have a 50% duty cycle for cycle slip
reduction to work. The charge pump current setting must also
be set to a minimum. See the Cycle Slip Reduction for Faster
Lock Times section for more information.
Clock Divider Mode
Bits[DB16:DB15] must be set to 1, 0 to activate phase resync or
0, 1 to activate fast lock. Setting Bits[DB16:DB15] to 0, 0
disables the clock divider. See Figure 22.
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of phase resync. See the Phase Resync section for
more information. It also sets the timeout counter for fast lock.
See the Fast Lock Timer and Register Sequences section for
more information.
REGISTER 4
Control Bits
With Bits[C3: C1] set to 1, 0, 0, Register 4 is programmed.
Figure 23 shows the input data format for programming this
register.
This register is reserved and has to be programmed with the
values as shown in Figure 23. Bits[DB31:DB24] and [DB22:DB3]
must be programmed to 0, while Bit DB23 must be set to 1.
REGISTER 5
Control Bits
With Bits[C3:C1] set to 1, 0, 1, Register 5 is programmed.
Figure 24 shows the input data form for programming this
register.
Lock Detect PIN Operation
Bits[DB23:DB22] set the operation of the lock detect pin (see
INITIALIZATION SEQUENCE
The following sequence of registers is the correct sequence for
initial power up of the ADF4151 after the correct application
of voltages to the supply pins:
1. Register 5
2. Register 4
3. Register 3
4. Register 2
5. Register 1
6. Register 0
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| ADF4151BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4152HVBCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4152HVBCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4153 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| ADF4153ABCPZ | 制造商:Analog Devices 功能描述:SINGLE RF F-N PLL 制造商:Analog Devices 功能描述:SINGLE RF F-N PLL - Trays 制造商:Analog Devices 功能描述:IC PLL FREQ SYNTHESIZER 20-LFCSP 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER 4GHZ 20 制造商:Analog Devices 功能描述:IC, FREQ SYNTHESIZER, 4GHZ, 20LFCSP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Single RF F-N PLL 制造商:Analog Devices 功能描述:PLL SYNTHESIZER, FREQUENCY, 4GHZ, LFCSP-20; PLL Type:Frequency Synthesis; Frequency:4GHz; Supply Current:20mA; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Digital IC Case Style:LFCSP; No. of Pins:20; Package / Case:20-LFCSP 制造商:Analog Devices 功能描述:IC, FREQ SYNTHESIZER, 4GHZ, 20LFCSP; Synthesizer Type:Frequency; Frequency:4GHz; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Supply Current:20mA; Digital IC Case Style:LFCSP; No. of Pins:20; Operating Temperature Min:-40C; ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:PLL SYNTHESIZER, FREQUENCY, 4GHZ, LFCSP-20; PLL Type:Frequency Synthesis; Frequency:4GHz; Supply Current:20mA; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; Digital IC Case Style:LFCSP; No. of Pins:20; Package / Case:20-LFCSP ;RoHS Compliant: Yes |
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