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參數(shù)資料
| 型號： | ADE7757AARZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | LEAD FREE, MS-012AC, SOIC-16 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 391K |
| 代理商： | ADE7757AARZ |
ADE7757A
Preliminary Technical Data
Rev. PrE | Page 4 of 24
Parameter
Value
Unit
Test Conditions/Comments
POWER SUPPLY
For specified performance
VDD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
IDD
5
mA max
Typically 4 mA
1 See the Terminology section for an explanation of specifications.
2 See plots in the Typical Performance Characteristics section.
3 Sample tested during initial release and after any redesign or process change that may affect this parameter.
TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 k, 0.5% ± 50 ppm/°C, TMIN to TMAX = –40°C to +85°C, unless
otherwise noted.
Sample tested during initial release and after any redesign or process change that may affect this parameter. See Figure 2.
Table 2.
Parameter
Specifications
Unit
Test Conditions/Comments
t11
120
ms
F1 and F2 pulse width (logic low).
t2
See Table 6
sec
Output pulse period. See the Transfer Function section.
t3
1/2 t2
sec
Time between F1 falling edge and F2 falling edge.
t41, 2
90
ms
CF pulse width (logic high).
t5
See Table 7
sec
CF pulse period. See the Transfer Function section.
t6
2
s
Minimum time between F1 and F2 pulses.
1 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.
2 The CF pulse is always 35 s in high frequency mode. See the Frequency Outputs section and Table 7.
F1
F2
CF
t1
t5
t4
t2
t6
t3
05330-002
Figure 2. Timing Diagram for Frequency Outputs
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