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參數(shù)資料
| 型號(hào)： | AD9985KSTZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/32頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 8BIT 140MSPS 80LQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | 串行 |
| 電源電壓： | 2.2 V ~ 3.45 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9985
Rev. 0 | Page 17 of 32
Hex
Address
Write and
Read or
Read Only
Bits
Default
Value
Register Name
Function
03H
R/W
7:3
01******
Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL
description.)
**001***
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
04H
R/W
7:3
10000***
Phase Adjust
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32)
05H
R/W
7:0
10000000
Clamp
Placement
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
06H
R/W
7:0
10000000
Clamp Duration
Number of clock periods that the clamp signal is actively clamping.
07H
R/W
7:0
00100000
Hsync Output
Pulsewidth
Sets the number of pixel clocks that HSOUT will remain active.
08H
R/W
7:0
10000000
Red Gain
09H
R/W
7:0
10000000
Green Gain
0AH
R/W
7:0
10000000
Blue Gain
Controls ADC input range (contrast) of each respective channel.
Greater values give less contrast.
0BH
R/W
7:1
1000000*
Red Offset
0CH
R/W
7:1
1000000*
Green Offset
0DH
R/W
7:1
1000000*
Blue Offset
Controls dc offset (brightness) of each respective channel. Greater
values decrease brightness.
0EH
R/W
7:0
0*******
Sync Control
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 6 in Register 0EH.)
*1******
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync signal
to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
**0*****
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
***0****
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 3. If set to Logic 0, the active interface is
selected via Bit 6 in Register 14H.
****0***
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active sync.
Logic 1 selects Sync-on-Green as the active sync. Note that the
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both
syncs are active. (Bits 1, 7 = Logic 1 in Register 14H.)
*****0**
Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.)
******0*
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select the
Vsync to be used via Bit 0. If set to Logic 0, the active interface is
selected via Bit 3 in Register 14H.
*******0
Bit 0 – Active Vsync Select. Logic 0 selects raw Vsync as the output
Vsync. Logic 1 selects sync separated Vsync as the output Vsync. Note
that the indicated Vsync will be used only if Bit 1 is set to Logic 1.
0FH
R/W
7:1
0*******
Bit 7 – Clamp Function. Chooses between Hsync for Clamp signal or
another external signal to be used for clamping. (Logic 0 = Hsync,
Logic 1 = Clamp.)
*1******
Bit 6 – Clamp Polarity. Valid only with external Clamp signal. (Logic 0 =
Active High, Logic 1 Selects Active Low.)
**0*****
Bit 5 – Coast Select. Logic 0 selects the coast input pins to be used for
the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
***0****
Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 3 in Register 0FH.)
****1***
Bit 3 – Coast Polarity. Selects polarity of external Coast signal. (Logic 0
= Active Low, Logic 1 = Active High.)
*****1**
Bit 2 – Seek Mode Override. (Logic 1 = Allow Low Power Mode, Logic 0
= Disallow Low Power Mode.)
******1*
Bit 1 – PWRDN. Full Chip Power-Down, Active Low. (Logic 0 = Full Chip
Power-Down, Logic 1 = Normal.)
10H
R/W
7:3
10111***
Sync-on-Green
Threshold
Sync-on-Green Threshold. Sets the voltage level of the Sync-on-Green
slicer’s comparator.
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