參數(shù)資料
型號(hào)： AD9985KSTZ-140
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE 8BIT 140MSPS 80LQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 串行
電源電壓： 2.2 V ~ 3.45 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9985
Rev. 0 | Page 22 of 32
0F
7
Clamp Input Signal Source
This bit determines the source of clamp timing.
Table 21. Clamp Input Signal Source Settings
Clamp Function
Function
0
Internally Generated Clamp Signal
1
Externally Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by
clamp placement and clamp duration. The clamp
position and duration is counted from the leading
edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
Clamp Polarity bit (Register 0FH, Bit 6).
The power-up default value is Clamp Function = 0.
0F
6
Clamp Input Signal Polarity
This bit determines the polarity of the externally
provided CLAMP signal.
Table 22. Clamp Input Signal Polarity Settings
Clamp Function
Function
1
Active Low
0
Active High
Logic 1 means that the circuit will clamp when
CLAMP is low, and it will pass the signal to the ADC
when CLAMP is high.
Logic 0 means that the circuit will clamp when
CLAMP is high, and it will pass the signal to the ADC
when CLAMP is low.
The power-up default value is Clamp Polarity = 1.
0F
5
Coast Select
This bit is used to select the active Coast source. The
choices are the Coast Input pin or Vsync. If Vsync is
selected, the additional decision of using the Vsync
input pin or the output from the sync separator needs
to be made (Register 0E, Bits 1, 0).
Table 23. Power-Down Settings
Select
Result
0
Coast Input Pin
1
Vsync (See above Text)
0F
4
Coast Input Polarity Override
This register is used to override the internal circuitry
that determines the polarity of the Coast signal going
into the PLL.
Table 24. Coast Input Polarity Override Settings
Override Bit
Result
0
Determined by Chip
1
Determined by User
The default for coast polarity override is 0.
0F
3
Coast Input Polarity
This bit indicates the polarity of the Coast signal that
is applied to the PLL COAST input.
Table 25. Coast Input Polarity Settings
Coast Polarity
Function
0
Active Low
1
Active High
Active Low means that the clock generator will ignore
Hsync inputs when Coast is low, and continue
operating at the same nominal frequency until Coast
goes high.
Active High means that the clock generator will ignore
Hsync inputs when Coast is high, and continue
operating at the same nominal frequency until Coast
goes low.
This function needs to be used along with the Coast
Polarity Override bit (Bit 4).
The power-up default value is 1.
0F
2
Seek Mode Override
This bit is used to either allow or disallow the low
power mode. The low power mode (Seek Mode)
occurs when there are no signals on any of the Sync
inputs.
Table 26. Seek Mode Override Settings
Select
Result
1
Allow Seek Mode
0
Disallow Seek Mode
The default for this register is 1.
0F
1
PWRDN
This bit is used to put the chip in full power-down. See
the Power Management section for details of which
blocks are powered down.
Table 27. Power-Down Settings
Select
Result
0
Power-Down
1
Normal Operation
10
7-3
Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the
Sync-on-Green slicer to be adjusted. This register
adjusts it in steps of 10 mV, with the minimum setting
equaling 10 mV (11111) and the maximum setting
equaling 330 mV (00000).
The default setting is 23, which corresponds to a
threshold value of 100 mV; for a threshold of 150 mV,
the setting should be 18.
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