參數(shù)資料
型號： AD9949KCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 8/36頁
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 40-LFCSP
標準包裝： 2,500
類型： CCD 信號處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP
包裝： 帶卷 (TR)
AD9949
Rev. B | Page 16 of 36
Table 12. HBLK Register Map
Address
Data Bit
Content
Default Value
(Hex)
Name
Description
40
[0]
0
HBLKDIR
HBLK Internal/External.
0 = Internal.
1 = External.
41
[0]
0
HBLKPOL
HBLK External Active Polarity.
0 = Active Low.
1 = Active High.
42
[0]
1
HBLKEXTMASK
HBLK External Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1High.
43
[3:0]
F
HBLKMASK
HBLK Internal Masking Polarity for Each Sequence 0 to 3.
0 = Mask H1 Low.
1 = Mask H1 High.
44
[23:0]
FFFFFF
HBLKTOG12_0
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
45
[23:0]
FFFFFF
HBLKTOG34_0
Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
46
[23:0]
FFFFFF
HBLKTOG56_0
Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
47
[23:0]
FFFFFF
HBLKTOG12_1
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
48
[23:0]
FFFFFF
HBLKTOG34_1
Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
49
[23:0]
FFFFFF
HBLKTOG56_1
Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4A
[23:0]
FFFFFF
HBLKTOG12_2
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4B
[23:0]
FFFFFF
HBLKTOG34_2
Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4C
[23:0]
FFFFFF
HBLKTOG56_2
Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4D
[23:0]
FFFFFF
HBLKTOG12_3
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4E
[23:0]
FFFFFF
HBLKTOG34_3
Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4F
[23:0]
FFFFFF
0
HBLKTOG56_3
HBLKSCP0
Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6[23:12].
HBLK Sequence-Change Position 0 (Hard-coded to 0).
50
[7:0]
0
HBLKSPTR
HBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
51
[11:0]
FFF
HBLKSCP1
HBLK Sequence-Change Position 1.
52
[11:0]
FFF
HBLKSCP2
HBLK Sequence-Change Position 2.
53
[11:0]
FFF
HBLKSCP3
HBLK Sequence-Change Position 3.
Table 13. H1 to H2, RG, SHP, SHD Register Map
Address
Data Bit
Content
Default Value
Name
Description
60
[12:0]
01001
H1CONTROL
H1 Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion).
H1 Positive Edge Location [6:1].
H1 Negative Edge Location [12:7].
61
[12:0]
00801
RGCONTROL
RG Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion).
RG Positive Edge Location [6:1].
RG Negative Edge Location [12:7].
62
[14:0]
0
DRVCONTROL
Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and RG
[14:12].
Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA,
3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.
63
[11:0]
00024
SAMPCONTROL
SHP/SHD Sample Control. SHP Sampling Location [5:0]. SHD Sampling
Location [11:6].
64
[5:0]
0
DOUTPHASE
DOUT Phase Control.
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