- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11659 > AD9949KCPZRL (Analog Devices Inc)IC CCD SIGNAL PROCESSOR 40-LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9949KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/36頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD9949
Rev. B | Page 31 of 36
DRIVING THE CLI INPUT
The AD9949’s master clock input (CLI) may be used in two
different configurations, depending on the application.
Figure 41 shows a typical dc-coupled input from the master
clock source. When the dc-coupled technique is used, the
master clock signal should be at standard 3 V CMOS logic
levels. As shown in Figure 42, a 1000 pF ac-coupling capacitor
may be used between the clock source and the CLI input. In this
configuration, the CLI input is self-biased to the proper dc volt-
age level of approximately 1.4 V. When the ac-coupled tech-
nique is used, the master clock signal can be as low as ±500 mV
in amplitude.
CCD IMAGER
SIGNAL
OUT
H2
RG
H3
H4
H1
H2
H1
RG
AD9949
CCDIN
03751-040
18
19
14
15
21
27
Figure 39. CCD Connections (2 H-Clock)
03751-041
CCD IMAGER
SIGNAL
OUT
H4
RG
H1
H2
H3
H4
H2
H1
H3
RG
AD9949
CCDIN
14
15
18
19
21
27
Figure 40. CCD Connections (4 H-Clock)
03751-042
CLI
AD9949
25
ASIC
MASTER CLOCK
Figure 41. CLI Connection, DC-Coupled
LPF
1nF
03751-
043
CLI
AD9949
25
ASIC
MASTER CLOCK
Figure 42. CLI Connection, AC-Coupled
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 43 shows an example CCD layout. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are
10 optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9949 horizontal signals for this CCD, three
sequences can be used. Figure 44 shows the first sequence that
should be used during vertical blanking. During this time, there
are no valid OB pixels from the sensor, so the CLPOB signal is
not used. PBLK may be enabled during this time, because no
valid data is available.
Figure 45 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loop of the AD9949.
Figure 46 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 2081204-7 | CONN JACK SMA BULKHEAD RG58 |
| 2081204-5 | CONN JACK SMA BULKHEAD RD316 |
| AD9948KCPZRL | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| AD22057R-REEL | IC AMP DIFF SNGL-SUP 8SOIC T/R |
| VE-JN2-IZ-B1 | CONVERTER MOD DC/DC 15V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9950KJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9950TJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9951 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9951/PCBZ | 制造商:Analog Devices 功能描述:AD9951 400 MSPS DDS W/ 14 BIT DAC EVALBD - Boxed Product (Development Kits) |
| AD9951PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。