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參數(shù)資料
| 型號： | AD9945KCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
–4–
AD9945
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
tCONV
25
ns
DATACLK High/Low Pulse Width
tADC
10
12.5
ns
SHP Pulse Width
tSHP
6.25
ns
SHD Pulse Width
tSHD
6.25
ns
CLPOB Pulse Width
*
tCOB
2
20
Pixels
SHP Rising Edge to SHD Falling Edge
tS1
6.25
ns
SHP Rising Edge to SHD Rising Edge
tS2
11.25
12.5
ns
Internal Clock Delay
tID
3ns
DATA OUTPUTS
Output Delay
tOD
9.5
ns
Pipeline Delay
10
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
*Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
(CL = 20 pF, fSAMP = 40 MHz, CCD Mode Timing in Figures 8 and 9, Serial Timing in Figures 4 and 5.)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9945 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
*
With
Respect
Parameter
To
Min
Max
Unit
AVDD
AVSS
–0.3
+3.9
V
DVDD
DVSS
–0.3
+3.9
V
DRVDD
DRVSS
–0.3
+3.9
V
Digital Outputs
DRVSS
–0.3
DRVDD + 0.3
V
SHP, SHD, DATACLK
DVSS
–0.3
DVDD + 0.3
V
CLPOB, PBLK
DVSS
–0.3
DVDD + 0.3
V
SCK, SL, SDATA
DVSS
–0.3
DVDD + 0.3
V
REFT, REFB, CCDIN
AVSS
–0.3
AVDD + 0.3
V
Junction Temperature
150
°C
Lead Temperature
300
°C
(10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operational
sections of this specication is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-Lead LFCSP Package
θJA = 27.7 °C/W
REV.
C
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