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參數資料
| 型號： | AD9945KCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 8/14頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 32-LFCSP |
| 標準包裝： | 1,500 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
AD9945
–3–
Parameter
Min
Typ
Max
Unit
Notes
CDS
Maximum Input Range before Saturation
*
1.0
Vp-p
Allowable CCD Reset Transient
*
500
mV
See Input Waveform in Footnote
Maximum CCD Black Pixel Amplitude
*
100
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
1024
Steps
Gain Monotonicity
Guaranteed
Gain Range
Minimum Gain
5.3
dB
Maximum Gain
40.0
41.5
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
256
Steps
Clamp Level
Measured at ADC Output
Minimum Clamp Level
0
LSB
Maximum Clamp Level
255
LSB
A/D CONVERTER
Resolution
12
Bits
Differential Nonlinearity (DNL)
±0.5
LSB
No Missing Codes
Guaranteed
Data Output Coding
Straight Binary
Full-Scale Input Voltage
2.0
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
V
Reference Bottom Voltage (REFB)
1.0
V
SYSTEM PERFORMANCE
Specifications Include Entire Signal Chain
Gain Range
Low Gain (VGA Code = 0)
5.3
dB
Maximum Gain (VGA Code = 1023)
40.0
41.5
dB
Gain Accuracy
1.0
dB
Peak Nonlinearity, 500 mV Input Signal
0.1
%
12 dB Gain Applied
Total Output Noise
1.2
LSB rms
AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR)
40
dB
*Input Signal Characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV TYP
OPTICAL BLACK PIXEL
1V TYP
INPUT SIGNAL RANGE
Specifications subject to change without notice.
SYSTEM SPECIFICATIONS
REV.
C
, AVDD = DVDD = DRVDD = 3.0 V, f
= 40 MHz, Register 0xD = 0x838,
unless otherwise noted.)
MAX
MIN
(T
to T
SAMP
See Variable Gain Amplifier section for VGA gain equation
Low Gain Mode
1.5
0
+1.5
dB
See Table 1, Internal Register Map, for register information
See Figure 7 for VGA Gain Curve
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