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參數(shù)資料
| 型號： | AD9945KCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 32-LFCSP |
| 標準包裝： | 1,500 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
AD9945
–9–
SERIAL INTERFACE
SDATA
SCK
SL
A2
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDS
tDH
tLS
tLH
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. ALL 12 DATA BITS D0 TO D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE
USED FOR THE UNDEFINED BITS.
D11
Figure 4. Serial Write Operation
SDATA
A0
A1
A2
D0
D1
D2
D3
D4
D5
D10
D11
SCK
SL
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 12-BIT DATA-WORD (ALL 12 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.
D0
D1
D10
D11
D0
...
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
...
1
16
23
4
567
8
9
10
15
18
17
28
27
30
29
31
Figure 5. Continuous Serial Write Operation to All Registers
REV.
C
A3
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相關代理商/技術參數(shù) |
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| AD9945KCPZRL72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 40 MHz CCD Signal Processor |
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