- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9945KCPZRL7 (Analog Devices Inc)IC CCD SIGNAL PROCESSOR 32-LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9945KCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)
–8–
AD9945
INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register
Address Bits
Name
Data Bits
Function
Operation
D0
Software Reset (0 = Normal Operation, 1 = Reset all registers to default)
D2, D1
Power-Down Modes (00 = Normal Power, 01 = Standby, 10 = Total Shutdown)
D3
OB Clamp Disable (0 = Clamp ON, 1 = Clamp OFF)
D5, D4
Test Mode. Should always be set to 00.
D6
PBLK Blanking Level (0 = Blank Output to Zero, 1 = Blank to OB Clamp Level)
Control
D0
SHP/SHD Input Polarity (0 = Active Low, 1 = Active High)
D1
DATACLK Input Polarity (0 = Active Low, 1 = Active High)
D2
CLPOB Input Polarity (0 = Active Low, 1 = Active High)
D3
PBLK Input Polarity (0 = Active Low, 1 = Active High)
D4
Three-State Data Outputs (0 = Outputs Active, 1 = Outputs Three-Stated)
D5
Data Output Latching (0 = Latched by DATACLK, 1 = Latch is Transparent)
D6
Data Output Coding (0 = Binary Output, 1 = Gray Code Output)
D11 to D7
Test Mode. Should always be set to 00000.
Clamp Level
D7 to D0
OB Clamp Level (0 = 0 LSB, 255 = 255 LSB)
VGA Gain
D9 to D0
VGA Gain (0 = 6 dB, 1023 = 40 dB)
REV.
C
A3 A2 A1 A0
0
1
0
1
0
1
Startup
1
0
1
D11 to D0
Required start-up write must be set to 0x838.
NOTE: All register values default to 0x0000 at power-up except clamp level, which defaults to 128 decimal (128 LSB clamp level).
Low Gain Mode. Normally set to 00. To enable low gain mode, set to 11. When low gain mode
is enabled, VGA Gain register must be set to all zeroes.
Test Mode. Should always be set to 000.
D8, D7
D11 to D9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9948KCPZ | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| AD9949KCPZ | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| AD9951YSVZ | IC DDS DAC 14BIT 1.8V 48-TQFP |
| AD9952YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
| AD9953YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9945KCPZRL72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 40 MHz CCD Signal Processor |
| AD9948 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9948AKCPZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9948AKCPZRL | 制造商:Analog Devices 功能描述: |
| AD9948KCP | 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MSPS, 3V ANALOG FRONT END - Bulk 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。