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參數(shù)資料
| 型號： | AD9898KCP-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 40/52頁 |
| 文件大?。?/td> | 557K |
| 代理商： | AD9898KCP-20 |
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REV. 0
–40–
AD9898
VSG TIMING
The VSG timing is controlled using the registers in Table XXIII.
Two unique preprogrammed VSG pulses can be configured
using the VSGTOG1_x (x = 0, 1) registers. As shown in
Figure 42, the period of the VSG pulse is set by programming
the VSGLEN register. The VSGSELx (x = 0, 1) can then be
used to point to either the VSGTOG1_0 or VSGTOG1_1 pulse.
1
2
3
0
VD
HD
13-BIT
ST COUNTER
(FIXED)
VSGx
1. VSGTOG1_x (x = 0, 1) REFERENCES THE 13-BIT ST COUNTER.
2. VSGACTLINE (PROGRAMMABLE AT MODE_REG (1)).
3. VSGLEN (PROGRAMMABLE AT SYS_REG (14)).
PROGRAMMABLE CLOCK POSITION
VSGTOG1_x (PROGRAMMABLE AT SYS_REG (13)).
VSGLEN
VSGACTLINE
1
Figure 42. Example of VSG Pulse
Table XXIII. VSG Registers
Register
Name
Bit
Width
Reference
Counter
Register Type
Range
Description
VSGMASK
6
Control (Addr 0x0A)
VSG Mask Control
(00 = VSG1 masked, VSG2 masked)
(02 = VSG1 not masked, VSG2 masked)
(08 = VSG1 masked, VSG2 not masked)
(0A = VSG1 not masked, VSG2 not masked)
VSG Output Enable Control
(0 = Disable VSG Outputs,
1 = Enable VSG Outputs)
VSG Sequence 1, Toggle Position 1
VSG Sequence 2, Toggle Position 1
VSG Pulsewidth
VSG1 Output Selector
(0 = VSGTOG1_0 applied on VSG1 output,
1 = VSGTOG1_1 applied on VSG1 output)
VSG2 Output Selector
(0 = VSGTOG1_0 applied on VSG2 output,
1 = VSGTOG1_1 applied on VSG2 output)
VSG Active Line
VSG_EN
1
Control (Addr 0x0B)
High/Low
VSGTOG1_0
VSGTOG1_1
VSGLEN
VSGSEL0
11
11
8
1
Sys_Reg(13)
Sys_Reg(13)
Sys_Reg(14)
Mode_Reg(1)
ST
ST
ST
0–8191 Pixels
0–8191 Pixels
0–255 Pixels
High/Low
VSGSEL1
1
Mode_Reg(1)
High/Low
VSGACTLINE
7
Mode_Reg(1)
0–128 Lines
Figure 42 also shows an example of the VSG pulse being output
in the fourth line by setting the VSGACTLINE = 3. The VSG1
and VSG2 pulses reference the 13-bit fixed ST counter, which
starts counting from the line set in the VSGACTLINE register.
The 13-bit counter allows for overlapping of the VSG pulse into
the next line, if needed.
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