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參數(shù)資料
| 型號： | AD9898KCP-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 33/52頁 |
| 文件大?。?/td> | 557K |
| 代理商： | AD9898KCP-20 |
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REV. 0
AD9898
–33–
Table XVI. Mode_A and Mode_B Registers for VTPx Selection
Register
Name
Bit
Width
Register
Type
Range
Description
VTPSEQPTR0
*
3
Mode_Reg(2)
Vertical Transfer Pulse Pointer Used in CCD Region 0
(0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3
4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line
5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line)
Vertical Transfer Pulse Pointer Used in CCD Region 1
(0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3
4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line
5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line)
Vertical Transfer Pulse Pointer Used in CCD Region 2
(0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3
4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line
5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line)
Vertical Transfer Pulse Pointer Used in CCD Region 3
(0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3
4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line
5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line)
Vertical Transfer Pulse Pointer Used in CCD Region 4
(0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3
4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line
5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line)
(0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3)
(0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3)
(0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3)
(0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3)
Number of VTP0 Pulse Repetitions within a Line
Number of VTP1 Pulse Repetitions within a Line
Number of VTP2 Pulse Repetitions within a Line
Number of VTP3 Pulse Repetitions within a Line
VTPSEQPTR1
*
3
Mode_Reg(2)
VTPSEQPTR2
*
3
Mode_Reg(2)
VTPSEQPTR3
*
3
Mode_Reg(2)
VTPSEQPTR4
*
3
Mode_Reg(2)
VTPSEL0
VTPSEL1
VTPSEL2
VTPSEL3
VTPREP0
VTPREP1
VTPREP2
VTPREP3
2
2
2
2
3
3
3
3
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(4)
Mode_Reg(4)
0–7
0–7
0–7
0–7
*
Registers 6 and 7 are not used.
Table XVII. Mode_A and Mode_B Registers for CCD Region Selection
Register
Name
Bit
Width
Register
Type
Range
Description
SCP1
SCP2
SCP3
SCP4
8
8
8
8
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(3)
0–255 lines
0–255 lines
0–255 lines
0–255 lines
Sequence Change Position 1
Sequence Change Position 2
Sequence Change Position 3
Sequence Change Position 4
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