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參數(shù)資料
| 型號： | AD9898KCP-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 557K |
| 代理商： | AD9898KCP-20 |
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REV. 0
–18–
AD9898
VD SYNCHRONOUS AND ASYNCHRONOUS REGISTER
OPERATION
There are two types of control registers, VD synchronous and
VD asynchronous, as indicated in the address column of Table I.
Register writes to synchronous and asynchronous type registers
operate differently, as described below. Writes to system, Mode_A,
and Mode_B registers occur asynchronously.
Asynchronous Register Operation
For VD asynchronous register writes, SDATA data is stored
directly into the serial register at the rising edge of SL. As a
result, register operation begins immediately after the rising
edge of SL.
VD Synchronous Register Operation
For VD synchronous type registers, SDATA data is temporarily
stored in a buffer register at the rising edge of SL. This data is
held in the buffer register until the next falling edge of VD is
applied. Once the next falling edge of VD occurs, the buffered
SDATA data is loaded into the serial register and the register
operation begins (see Figure 9).
All control registers at the following addresses are VD Synchro-
nous type registers—Addr: 0x0A, 0x0B, 0x0C, 0x0D, and 0x0E
(see Table I).
VD
HD
CLI
OPERATION OF VD SYNCHRONOUS TYPE
REGISTER WRITES BEGIN AT THE NEXT VD
FALLING EDGE.
PROGRAMMING OF VD SYNCHRONOUS
TYPE REGISTERS MUST BE COMPLETED
AT LEAST 4 CLI CYCLES BEFORE THE
FALLING EDGE OF VD.
Figure 9. VD Synchronous Type Register Writes
SDATA
SCK
SL
A
A
A
A
A
A
A
A
N
N
N
N
N
N
N
N
D
D
D
D
D
D
D
D
D
D
8-BIT
ADDRESS
NUMBER OF 32-BIT
DATA WRITES (N)
D
D
D
D
D
D
D
DATA 2 [31:0]
D
D
D
D
DATA N [31:0]
DATA 1 [31:0]
NUMBER WRITES N [23:0]
ADDRESS [7:0]
DATA 2 [31:0]
DATA N [31:0]
1
1
1
2
DATA 1 [31:0]
1. ALL SL PULSES ARE IGNORED UNTIL THE LSB OF THE LAST DATA N WORD IS CLOCKED IN.
2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.
Figure 8. System and Mode Register Writes
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