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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD9878BSTZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 32/36闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FRONT-END MIXED-SGNL 100-LQFP |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | AD9878BSTZ Discontinuation 21/Nov/2011 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閫氶亾鏁�(sh霉)锛� | 4 |
| 鍔熺巼锛堢摝鐗癸級锛� | 673mW |
| 闆诲 - 闆绘簮锛屾ā鎿細 | 3.3V |
| 闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 | 3.3V |
| 灏佽/澶栨锛� | 100-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-LQFP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
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AD9878
Rev. A | Page 5 of 36
PARAMETER
Temp
Test Level
Min
Typ
Max
Unit
Dynamic Performance (AIN = 0.5 dBFS, f = 50 MHz)
Signal-to-Noise and Distortion (SINAD)
Full
II
54.8
57.8
dB
Effective Number of Bits (ENOB)
Full
II
8.8
9.3
Bits
Total Harmonic Distortion (THD)
Full
II
63.3
56.9
dB
Spurious-Free Dynamic Range (SFDR)
Full
II
56.9
63.7
dB
12-BIT ADC CHARACTERISTICS
Resolution
N/A
12
Bits
Maximum Conversion Rate
Full
II
29
MHz
Pipeline Delay
N/A
5.5
ADC cycles
Analog Input
Input Voltage Range
Full
III
2
VPPD
Differential Input Impedance
25掳C
III
4||2
k||pF
Aperture Delay
25掳C
III
2.0
ns
Aperture Jitter
25掳C
III
1.2
ps rms
Full Power Bandwidth
25掳C
III
85
MHz
Input Referred Noise
25掳C
III
75
V
Reference Voltage Error, REFT12 to REFB12 (1 V)
Full
I
100
卤16
+100
mV
Dynamic Performance (AIN = 0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Full
II
61.0
67
dB
Effective Number of Bits (ENOBs)
Full
II
9.8
10.8
Bits
Signal-to-Noise Ratio (SNR)
Full
II
64.2
66
dB
Total Harmonic Distortion (THD)
Full
II
72.7
61.7
dB
Spurious-Free Dynamic Range (SFDR)
Full
II
62.8
74.6
dB
ADC Sample Clock = PLL
Signal-to-Noise and Distortion (SINAD)
Full
II
60.4
64.4
dB
Effective Number of Bits (ENOB)
Full
II
9.74
10.4
Bits
Signal-to-Noise Ratio (SNR)
Full
II
62.4
65.1
dB
Total Harmonic Distortion (THD)
Full
II
72.7
61.8
dB
Spurious-Free Dynamic Range (SFDR)
Full
II
62.7
74.6
dB
Dynamic Performance (AIN = 0.5 dBFS, f = 50 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Full
II
61.0
65.2
dB
Effective Number of Bits (ENOB)
Full
II
9.8
10.5
Bits
Signal-to-Noise Ratio (SNR)
Full
II
64.2
67.4
dB
Total Harmonic Distortion (THD)
Full
II
72.8
61.8
dB
Spurious-Free Dynamic Range (SFDR)
Full
II
62.8
74.6
dB
Differential Phase
25掳C
III
<0.1
Degrees
Differential Gain
25掳C
III
<1
LSB
VIDEO ADC PERFORMANCE (AIN = 0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Full
II
46.7
53
dB
Signal-to-Noise Ratio (SNR)
Full
II
54.3
63.2
Bits
Total Harmonic Distortion (THD)
Full
II
50.2
45.9
dB
Spurious-Free Dynamic Range (SFDR)
Full
II
45.9
50
dB
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (5 MHz Analog Output)
Isolation Between Tx and 10-Bit ADC
25掳C
III
>60
dB
Isolation Between Tx and 12-Bit ADCs
25掳C
III
>80
dB
ADC-to-ADC Isolation (AIN = 鈥�0.5 dBFS, f = 5 MHz)
Isolation Between IF10 and IF12A/B
25掳C
III
>85
dB
Isolation Between IF12A and IF12B
25掳C
III
>85
dB
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AD9879BSZ | IC PROCESSOR FRONT END 100MQFP |
| AD9901KQ | IC PHASE/FREQ DISCRIMR 14-CDIP |
| AD9920ABBCZRL | IC PROCESSOR CCD 12BIT 105CSPBGA |
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
| ADADC71KD | IC ADC 16BIT HIGH RES 32-CDIP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD9878-EB | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:EVAL KIT FOR MIXED-SGNL FRONT END FOR BROADBAND APPLICATIONS - Bulk |
| AD9879 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9879_05 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9879BS | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪: |
| AD9879BSZ | 鍔熻兘鎻忚堪:IC PROCESSOR FRONT END 100MQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃摤鍓嶇 (AFE) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 浣嶆暩(sh霉):- 閫氶亾鏁�(sh霉):2 鍔熺巼锛堢摝鐗癸級:- 闆诲 - 闆绘簮锛屾ā鎿�:3 V ~ 3.6 V 闆诲 - 闆绘簮锛屾暩(sh霉)瀛�:3 V ~ 3.6 V 灏佽/澶栨:32-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:32-QFN锛�5x5锛� 鍖呰:甯跺嵎 (TR) |
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