參數(shù)資料
型號(hào)： AD9878BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/36頁(yè)
文件大小： 0K
描述： IC FRONT-END MIXED-SGNL 100-LQFP
產(chǎn)品變化通告： AD9878BSTZ Discontinuation 21/Nov/2011
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 673mW
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 3.3V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
AD9878
Rev. A | Page 20 of 36
THEORY OF OPERATION
For a general understanding of the AD9878, refer to Figure 23, a
block diagram of the device architecture. The device consists of a
transmit path, receive path, and auxiliary functions, such as a PLL,
a ∑- DAC, a serial control port, and a cable amplifier interface.
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a 12-bit
current output DAC.
The receive path contains a 10-bit ADC and dual 12-bit ADCs.
All internally required clocks and an output system clock are
generated by the PLL from a single crystal or clock input.
The 12-bit and 10-bit IF ADCs can convert direct IF inputs of
up to 70 MHz and run at sample rates of up to 29 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9878 to process an NTSC and a QAM
channel simultaneously.
The programmable ∑- DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltage-
controlled tuners. The CA port provides an interface to the
AD832x family of programmable gain amplifier (PGA) cable
drivers, enabling host processor control via the MxFE serial
port (SPORT).
03277-007
TxIQ[5:0]
TxSYNC
MCLK
REFCLK
CA PORT
PROFILE
SDIO
IF10[4:0]
RxSYNC
IF12[11:0]
FSADJ
XTAL
OSCIN
Σ- OUTPUT
FLAG[2:1]
IF10 INPUT
IF12B INPUT
VIDEO IN
6
3
12
AD9878
DATA
ASSEMBLER
QUADRATURE
MODULATOR
FIR LPF
CIC LPF
COS
SIN
DAC GAIN CONTROL
PLL
OSCIN
× M
DDS
MUX
CA
INTERFACE
PROFILE
SELECT
SERIAL
INTERFACE
12
4
SINC–1
MUX
DAC
IF10
IF12
ADC
10
12
4
5
12
I
Q
Rx PORT
Tx OUTPUT
Σ- INPUT
4
8
FLAG0
SINC–1
BYPASS
(
fOSCIN)
(
fOSCIN)
(
fMCLK)
MUX
12
ADC
MUX
IF12A INPUT
DAC
+
–
CLAMP LEVEL
Σ-
÷R
÷8
÷2
(
fIQCLK)
(
fSYSCLK)
(
fOSCIN)
÷4
Figure 23. AD9878 Block Diagram
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AD9879BSZ 功能描述:IC PROCESSOR FRONT END 100MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR)
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