參數(shù)資料
型號： AD9849AKSTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 9/32頁
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC 12BIT 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
類型： CCD 信號處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
REV. A
AD9848/AD9849
–17–
Bit
Default
Address
Content
Width
Value
Register Name
Register Description
PBLK # Bits 146
C5
[0]
1
01
pblkdir
PBLK Internal/External (0 = Internal, 1 = External)
C6
[0]
1
00
pblkpol
PBLK External Active Polarity (0 = Low Active,
1 = High Active)
C7
[0]
1
01
pblkspol0
Sequence #0: Start Polarity for PBLK
C8
[5:0]
6
3D
pblktog1_0[5:0]
Sequence #0: Toggle Position 1 for PBLK
C9
[5:0]
6
00
pblktog1_0[11:6]
CA
[5:0]
6
2A
pblkbtog2_0[5:0]
Sequence #0: Toggle Position 2 for PBLK
CB
[5:0]
6
06
pblkbtog2_0[11:6]
CC
[0]
1
00
pblkspol1
Sequence #1: Start Polarity for PBLK
CD
[5:0]
6
2A
pblktog1_1[5:0]
Sequence #1: Toggle Position 1 for PBLK
CE
[5:0]
6
06
pblktog1_1[11:6]
CF
[5:0]
6
3F
pblktog2_1[5:0]
Sequence #1: Toggle Position 2 for PBLK
D0
[5:0]
6
3F
pblktog2_1[11:6]
D1
[0]
1
00
pblkspol2
Sequence #2: Start Polarity for PBLK
D2
[5:0]
6
3F
pblktog1_2[5:0]
Sequence #2: Toggle Position 1 for PBLK
D3
[5:0]
6
3F
pblktog1_2[11:6]
D4
[5:0]
6
3F
pblktog2_2[5:0]
Sequence #2: Toggle Position 2 for PBLK
D5
[5:0]
6
3F
pblktog2_2[11:6]
D6
[0]
1
01
pblkspol3
Sequence #3: Start Polarity for PBLK
D7
[5:0]
6
3F
pblktog1_3[5:0]
Sequence #3: Toggle Position 1 for PBLK
D8
[5:0]
6
3F
pblktog1_3[11:6]
D9
[5:0]
6
3F
pblktog2_3[5:0]
Sequence #3: Toggle Position 2 for PBLK
DA
[5:0]
6
3F
pblktog2_3[11:6]
000
pblkscp0
PBLK Sequence-Change-Position #0 (Hardcoded to 0)
DB
[1:0]
2
02
pblksptr0
PBLK Sequence Pointer for SCP #0
DC
[5:0]
6
01
pblkscp1[5:0]
PBLK Sequence-Change-Position #1
DD
[5:0]
6
00
pblkscp1[11:6]
DE
[1:0]
2
01
pblksptr1
PBLK Sequence Pointer for SCP #1
DF
[5:0]
6
02
pblkscp2[5:0]
PBLK Sequence-Change-Position #2
E0
[5:0]
6
00
pblkscp2[11:6]
E1
[1:0]
2
00
pblksptr2
PBLK Sequence Pointer for SCP #2
E2
[5:0]
6
37
pblkscp3[5:0]
PBLK Sequence-Change-Position #3
E3
[5:0]
6
03
pblkscp3[11:6]
E4
[1:0]
2
02
pblksptr3
PBLK Sequence Pointer for SCP #3
H1–H4, RG, SHP, SHD # Bits 53
E5
[0]
1
00
h1pol
H1/H2 Polarity Control (0 = No Inversion, 1 = Inversion)
E6
[5:0]
6
00
h1posloc
H1 Positive Edge Location
E7
[5:0]
6
20
h1negloc
H1 Negative Edge Location
E8
[2:0]
3
03
h1drv
H1 Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
E9
[2:0]
3
03
h2drv
H2 Drive Strength
EA
[2:0]
3
03
h3drv
H3 Drive Strength
EB
[2:0]
3
03
h4drv
H4 Drive Strength
EC
[0]
1
00
rgpol
RG Polarity Control (0 = No Inversion, 1 = Inversion)
ED
[5:0]
6
00
rgposloc
RG Positive Edge Location
EE
[5:0]
6
10
rgnegloc
RG Negative Edge Location
EF
[2:0]
3
02
rgdrv
RG Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA, 3 = 10.5 mA,
4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
F0
[5:0]
6
24
shpposloc
SHP (Positive) Edge Sampling Location
F1
[5:0]
6
00
shdposloc
SHD (Positive) Edge Sampling Location
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