參數(shù)資料
型號(hào)： AD9849AKSTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 13/32頁
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC 12BIT 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
REV. A
AD9848/AD9849
–20–
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9848/
AD9849 features on-chip output drivers for the RG and H1–H4
outputs. These drivers are powerful enough to directly drive the
CCD inputs. The H-driver current can be adjusted for optimum
rise/fall time into a particular load by using the DRV registers.
The RG drive current is adjustable using the RGDRV register.
Each 3-bit DRV register is adjustable in 3.5 mA increments, with
the minimum setting of 0 equal to OFF or three-state, and the
maximum setting of 7 equal to 24.5 mA.
As shown in Figure 7, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than l ns, which is significantly less than the typical rise time
driving the CCD load. This results in a H1/H2 crossover voltage
at approximately 50% of the output swing. The crossover voltage
is not programmable.
Digital Data Outputs
The AD9848/AD9849 data output phase is programmable
using the DOUTPHASE register. Any edge from 0 to 47 may
be programmed, as shown in Figure 8.
HORIZONTAL CLAMPING AND BLANKING
The AD9848/AD9849’s horizontal clamping and blanking
pulses are fully programmable to suit a variety of applications.
As with the vertical timing generation, individual sequences are
defined for each signal and are then organized into multiple
regions during image readout. This allows the dark pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate different image transfer timing and high speed
line shifts.
Table II. H1–H4, RG, SHP, SHD Timing Parameters
Register Name
Length
Range
Description
POL
1b
High/Low
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
POSLOC
6b
0–47 Edge Location
Positive Edge Location for H1, H3, and RG
Sample Location for SHP, SHD
NEGLOC
6b
0–47 Edge Location
Negative Edge Location for H1, H3, and RG
DRV
3b
0–7 Current Steps
Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)
Table III. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I0 to 11
0 to 11
000000 to 001011
II
12 to 23
16 to 27
010000 to 011011
III
24 to 35
32 to 43
100000 to 101011
IV
36 to 47
48 to 59
110000 to 111011
FIXED CROSSOVER VOLTAGE
H1/H3
H2/H4
tPD
H2/H4
H1/H3
tRISE
tPD
tRISE
<<
Figure 7. H-Clock Inverse Phase Relationship
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
P[0]
P[48] = P[0]
CLI
1 PIXEL PERIOD
P[12]
P[24]
P[36]
DOUT
tOD
Figure 8. Digital Output Phase Adjustment
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