參數(shù)資料
型號： AD9848KST
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： CCD Signal Processors with Integrated Timing Driver
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, LQFP-48
文件頁數(shù)： 6/36頁
文件大?。?/td> 347K
代理商： AD9848KST
REV. 0
–6–
AD9848/AD9849
TIMING SPECIFICATIONS
(C
L
= 20 pF, f
CLI
= 20 MHz [AD9848] or 30 MHz [AD9849], Serial Timing in Figure 3, unless
otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI), AD9848
CLI Clock Period
CLI High/Low Pulsewidth
Delay From CLI to Internal Pixel Period Position
t
CLI
t
ADC
t
CLIDLY
50
25
ns
ns
ns
6
MASTER CLOCK (CLI), AD9849
CLI Clock Period
CLI High/Low Pulsewidth
t
CONV
t
ADC
33.33
16.67
ns
ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth
CLPOB Pulsewidth
1
t
CDM
t
COB
4
2
10
20
Pixels
Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge (AD9848)
SHP Rising Edge to SHD Rising Edge (AD9849)
t
S1
t
S1
20
13
ns
ns
DATA OUTPUTS
Output Delay from Programmed Edge
Pipeline Delay
t
OD
6
9
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
NOTES
1
Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
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