參數(shù)資料
型號: AD9848KST
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: CCD Signal Processors with Integrated Timing Driver
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁數(shù): 25/36頁
文件大?。?/td> 347K
代理商: AD9848KST
REV. 0
AD9848/AD9849
–25–
POWER-UP PROCEDURE
VDD
(INPUT)
SERIAL
WRITES
VD
(OUTPUT)
1 H
ODD FIELD
EVEN FIELD
...
...
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS
UPDATED AT VD/HD EDGE
H1/H3, RG
H2/H4
t
PWR
CLI
(INPUT)
HD
(OUTPUT)
1V
...
...
Figure 14. Recommended Power-Up Sequence
Recommended Power-Up Sequence
When the AD9848 and AD9849 are powered up, the following sequence is recommended (refer to Figure 14 for each step).
1. Turn on power supplies for AD9848/AD9849.
2. Apply the master clock input CLI, VD, and HD.
3. The Precision Timing core must be reset by writing a “0” to the TGCORE_RSTB register (addr x026) followed by writing
a “l(fā)” to the TGCORE_RSTB register. This will start the internal timing core operation.
4. Write a “1” to the PREVENTUPDATE register (addr x01B). This will prevent the updating of the serial register data.
5. Write to desired registers to configure high speed timing and horizontal timing.
6. Write a “1” to the OUT_CONT register (addr x016). This will allow the outputs to become active after the next VD/HD
rising edge.
7. Write a “0” to the PREVENTUPDATE register (addr x01B). This will allow the serial information to be updated at next
VD/HD falling edge.
8. The next VD/HD falling edge allows register updates to occur, including OUT_CONT, which enables all clock outputs.
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