參數(shù)資料
型號: AD9848KST
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: CCD Signal Processors with Integrated Timing Driver
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁數(shù): 27/36頁
文件大?。?/td> 347K
代理商: AD9848KST
REV. 0
AD9848/AD9849
–27–
2
2
0
3
3
1
1
VD
NOTES
1. VD FALLING EDGE WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0101" LINE.
2. HD FALLING EDGES WILL ALTERNATE THE
PxGA
GAIN REGISTER STEERING BETWEEN "0101" AND "2323" LINES.
3. FLD STATUS IS IGNORED.
HD
1
1
0
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
0
2
2
0
3
3
1
1
1
1
0
0
0
0
Figure 16a. Mosaic Separate Mode
0
0
0
1
1
1
1
VD
NOTES
1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0101" LINE.
2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "2323" LINE.
3. HD FALLING EDGES WILL RESET THE
PxGA
GAIN REGISTER STEERING TO EITHER "0" (FLD = ODD) OR "2" (FLD = EVEN).
HD
1
1
0
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
0
2
2
2
3
3
3
3
3
3
2
2
2
0
Figure 16b. Mosaic Interlaced Mode
1
1
0
2
2
1
1
VD
NOTES
1. VD FALLING EDGE WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0101" LINE.
2. HD FALLING EDGES WILL ALTERNATE THE
PxGA
GAIN REGISTER STEERING BETWEEN "0101" AND "1212" LINES.
3. ALL FIELDS WILL HAVE THE SAME
PxGA
GAIN STEERING PATTERN (FLD STATUS IS IGNORED).
HD
1
1
0
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
0
1
1
0
2
2
1
1
1
1
0
0
0
0
Figure 16c. Mosaic Repeat Mode
0
2
0
1
0
0
1
VD
NOTES
1. EACH LINE FOLLOWS "012012" STEERING PATTERN.
2. VD AND HD FALLING EDGES WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0".
3. FLD STATUS IS IGNORED.
HD
1
0
2
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
2
0
2
0
1
0
0
1
1
0
2
0
2
0
Figure 16d. Three-Color Mode
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